EDN Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: a2f86af

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.960s	58.713us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.530s	107.345us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.640s	25.734us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.030s	350.201us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.720s	73.896us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.950s	67.335us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.640s	25.734us	1	1	100.00
		edn_csr_aliasing	1.720s	73.896us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.100s	44.551us	1	1	100.00
V2	csrng_commands	edn_genbits	2.100s	44.551us	1	1	100.00
V2	genbits	edn_genbits	2.100s	44.551us	1	1	100.00
V2	interrupts	edn_intr	1.630s	39.811us	1	1	100.00
V2	alerts	edn_alert	1.830s	27.873us	1	1	100.00
V2	errs	edn_err	1.640s	32.059us	1	1	100.00
V2	disable	edn_disable	1.640s	23.240us	1	1	100.00
		edn_disable_auto_req_mode	2.300s	73.276us	1	1	100.00
V2	stress_all	edn_stress_all	5.140s	820.992us	1	1	100.00
V2	intr_test	edn_intr_test	1.460s	13.182us	1	1	100.00
V2	alert_test	edn_alert_test	1.780s	33.250us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.420s	162.333us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.420s	162.333us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.530s	107.345us	1	1	100.00
		edn_csr_rw	1.640s	25.734us	1	1	100.00
		edn_csr_aliasing	1.720s	73.896us	1	1	100.00
		edn_same_csr_outstanding	1.920s	60.678us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.530s	107.345us	1	1	100.00
		edn_csr_rw	1.640s	25.734us	1	1	100.00
		edn_csr_aliasing	1.720s	73.896us	1	1	100.00
		edn_same_csr_outstanding	1.920s	60.678us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	10.130s	1.194ms	1	1	100.00
		edn_tl_intg_err	2.350s	161.225us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.630s	28.250us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.830s	27.873us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	10.130s	1.194ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	10.130s	1.194ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	10.130s	1.194ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	10.130s	1.194ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.830s	27.873us	1	1	100.00
		edn_sec_cm	10.130s	1.194ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.830s	27.873us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.350s	161.225us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	44.320s	6.178ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00