HMAC Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: a2f86af

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.230s 275.569us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.570s 87.452us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.470s 36.786us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.380s 289.766us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.970s 988.345us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.010s 103.803us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.470s 36.786us 1 1 100.00
hmac_csr_aliasing 6.970s 988.345us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 52.430s 17.121ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.313m 1.774ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.158m 6.558ms 1 1 100.00
hmac_test_sha384_vectors 19.260s 247.663us 1 1 100.00
hmac_test_sha512_vectors 18.540s 926.198us 1 1 100.00
hmac_test_hmac256_vectors 7.540s 502.028us 1 1 100.00
hmac_test_hmac384_vectors 7.290s 3.544ms 1 1 100.00
hmac_test_hmac512_vectors 8.650s 953.063us 1 1 100.00
V2 burst_wr hmac_burst_wr 18.190s 512.133us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 4.681m 5.493ms 1 1 100.00
V2 error hmac_error 4.670s 325.377us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 31.110s 771.942us 1 1 100.00
V2 save_and_restore hmac_smoke 2.230s 275.569us 1 1 100.00
hmac_long_msg 52.430s 17.121ms 1 1 100.00
hmac_back_pressure 1.313m 1.774ms 1 1 100.00
hmac_datapath_stress 4.681m 5.493ms 1 1 100.00
hmac_burst_wr 18.190s 512.133us 1 1 100.00
hmac_stress_all 6.608m 28.262ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.230s 275.569us 1 1 100.00
hmac_long_msg 52.430s 17.121ms 1 1 100.00
hmac_back_pressure 1.313m 1.774ms 1 1 100.00
hmac_datapath_stress 4.681m 5.493ms 1 1 100.00
hmac_wipe_secret 31.110s 771.942us 1 1 100.00
hmac_test_sha256_vectors 3.158m 6.558ms 1 1 100.00
hmac_test_sha384_vectors 19.260s 247.663us 1 1 100.00
hmac_test_sha512_vectors 18.540s 926.198us 1 1 100.00
hmac_test_hmac256_vectors 7.540s 502.028us 1 1 100.00
hmac_test_hmac384_vectors 7.290s 3.544ms 1 1 100.00
hmac_test_hmac512_vectors 8.650s 953.063us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.230s 275.569us 1 1 100.00
hmac_long_msg 52.430s 17.121ms 1 1 100.00
hmac_back_pressure 1.313m 1.774ms 1 1 100.00
hmac_datapath_stress 4.681m 5.493ms 1 1 100.00
hmac_burst_wr 18.190s 512.133us 1 1 100.00
hmac_error 4.670s 325.377us 1 1 100.00
hmac_wipe_secret 31.110s 771.942us 1 1 100.00
hmac_test_sha256_vectors 3.158m 6.558ms 1 1 100.00
hmac_test_sha384_vectors 19.260s 247.663us 1 1 100.00
hmac_test_sha512_vectors 18.540s 926.198us 1 1 100.00
hmac_test_hmac256_vectors 7.540s 502.028us 1 1 100.00
hmac_test_hmac384_vectors 7.290s 3.544ms 1 1 100.00
hmac_test_hmac512_vectors 8.650s 953.063us 1 1 100.00
hmac_stress_all 6.608m 28.262ms 1 1 100.00
V2 stress_all hmac_stress_all 6.608m 28.262ms 1 1 100.00
V2 alert_test hmac_alert_test 1.490s 68.597us 1 1 100.00
V2 intr_test hmac_intr_test 1.450s 173.810us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.680s 347.289us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.680s 347.289us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.570s 87.452us 1 1 100.00
hmac_csr_rw 1.470s 36.786us 1 1 100.00
hmac_csr_aliasing 6.970s 988.345us 1 1 100.00
hmac_same_csr_outstanding 1.920s 22.551us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.570s 87.452us 1 1 100.00
hmac_csr_rw 1.470s 36.786us 1 1 100.00
hmac_csr_aliasing 6.970s 988.345us 1 1 100.00
hmac_same_csr_outstanding 1.920s 22.551us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.620s 145.739us 1 1 100.00
hmac_tl_intg_err 3.100s 785.253us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.100s 785.253us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.230s 275.569us 1 1 100.00
V3 stress_reset hmac_stress_reset 4.930s 220.885us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 19.740s 1.312ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.590s 18.753us 1 1 100.00
TOTAL 28 28 100.00