I2C Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: `a2f86af`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	21.970s	1.465ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.900s	2.862ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.540s	57.735us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.600s	19.137us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.480s	224.424us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.500s	107.834us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.480s	122.649us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.600s	19.137us	1	1	100.00
		i2c_csr_aliasing	2.500s	107.834us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.050s	144.064us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	5.394m	39.507ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	12.685m	24.900ms	1	1	100.00
V2	host_override	i2c_host_override	1.700s	16.914us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.001m	3.497ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	42.340s	3.852ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.950s	1.074ms	1	1	100.00
		i2c_host_fifo_fmt_empty	10.630s	1.002ms	1	1	100.00
		i2c_host_fifo_reset_rx	4.020s	456.248us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.207m	19.293ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	18.190s	539.792us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.590s	131.049us	0	1	0.00
V2	target_glitch	i2c_target_glitch	8.510s	4.855ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	20.320s	18.597ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.170s	821.962us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	18.300s	565.748us	1	1	100.00
		i2c_target_intr_smoke	4.010s	1.538ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.040s	604.048us	1	1	100.00
		i2c_target_fifo_reset_tx	2.800s	741.607us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	13.550s	7.059ms	1	1	100.00
		i2c_target_stress_rd	18.300s	565.748us	1	1	100.00
		i2c_target_intr_stress_wr	38.320s	23.464ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.000s	1.302ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	10.310s	2.483ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.030s	4.949ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.500s	526.527us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.870s	361.090us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.980s	433.592us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	12.685m	24.900ms	1	1	100.00
		i2c_host_perf_precise	2.020s	222.114us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	18.190s	539.792us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.190s	279.038us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.270s	2.145ms	1	1	100.00
		i2c_target_nack_acqfull_addr	3.070s	2.376ms	1	1	100.00
		i2c_target_nack_txstretch	2.260s	342.067us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	11.680s	342.211us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.510s	392.670us	1	1	100.00
V2	alert_test	i2c_alert_test	1.480s	25.096us	1	1	100.00
V2	intr_test	i2c_intr_test	1.740s	37.480us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.420s	172.812us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.420s	172.812us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.540s	57.735us	1	1	100.00
		i2c_csr_rw	1.600s	19.137us	1	1	100.00
		i2c_csr_aliasing	2.500s	107.834us	1	1	100.00
		i2c_same_csr_outstanding	2.050s	77.109us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.540s	57.735us	1	1	100.00
		i2c_csr_rw	1.600s	19.137us	1	1	100.00
		i2c_csr_aliasing	2.500s	107.834us	1	1	100.00
		i2c_same_csr_outstanding	2.050s	77.109us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.850s	361.553us	1	1	100.00
		i2c_sec_cm	2.070s	73.274us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.850s	361.553us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	58.800s	22.960ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.400s	497.699us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	8.770s	608.303us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.63193233521664775011575313238492937280177689719993419130288832778455315828796
Line 222, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 39507411085 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2280432

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.24899934987399008424236066767967487500372735495094671361298576045863862228522
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 131049441 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @26405

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.77176993442535084881088958300771100202558988379631305960040460038364876131921
    Line 105, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22959699708 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 22959699708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.110348218045644202776111232181754442244453506870233533670096254177748528206168
    Line 90, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 608303096 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 608303096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.112153428978428803368008133424865915428318567419115997913052728016378267279584
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 497698561 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 205 [0xcd])
  UVM_INFO @ 497698561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```