KEYMGR Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: `a2f86af`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	4.140s	152.288us	1	1	100.00
V1	random	keymgr_random	4.290s	108.951us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.960s	60.440us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.860s	20.958us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.800s	265.996us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	6.940s	1.489ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.070s	30.500us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.860s	20.958us	0	1	0.00
		keymgr_csr_aliasing	6.940s	1.489ms	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	3.520s	195.696us	1	1	100.00
V2	sideload	keymgr_sideload	8.490s	1.667ms	1	1	100.00
		keymgr_sideload_kmac	3.290s	366.506us	1	1	100.00
		keymgr_sideload_aes	3.080s	272.640us	1	1	100.00
		keymgr_sideload_otbn	3.520s	132.604us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.230s	90.612us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	4.200s	610.205us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.850s	141.093us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	5.860s	451.310us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	30.990s	9.206ms	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.200s	38.084us	1	1	100.00
V2	stress_all	keymgr_stress_all	14.320s	941.575us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.940s	13.500us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.680s	11.655us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.030s	34.417us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.030s	34.417us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.960s	60.440us	1	1	100.00
		keymgr_csr_rw	1.860s	20.958us	0	1	0.00
		keymgr_csr_aliasing	6.940s	1.489ms	1	1	100.00
		keymgr_same_csr_outstanding	3.650s	89.825us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.960s	60.440us	1	1	100.00
		keymgr_csr_rw	1.860s	20.958us	0	1	0.00
		keymgr_csr_aliasing	6.940s	1.489ms	1	1	100.00
		keymgr_same_csr_outstanding	3.650s	89.825us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	10.470s	529.063us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	10.470s	529.063us	1	1	100.00
		keymgr_tl_intg_err	5.660s	156.012us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.940s	872.148us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.940s	872.148us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.940s	872.148us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.940s	872.148us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.790s	15.137us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	10.470s	529.063us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	10.470s	529.063us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.660s	156.012us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.940s	872.148us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.520s	195.696us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.290s	108.951us	1	1	100.00
		keymgr_csr_rw	1.860s	20.958us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.290s	108.951us	1	1	100.00
		keymgr_csr_rw	1.860s	20.958us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.290s	108.951us	1	1	100.00
		keymgr_csr_rw	1.860s	20.958us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	4.200s	610.205us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	30.990s	9.206ms	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	30.990s	9.206ms	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.290s	108.951us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.520s	54.635us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	10.470s	529.063us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	10.470s	529.063us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	10.470s	529.063us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.310s	61.688us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	4.200s	610.205us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	10.470s	529.063us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	10.470s	529.063us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	10.470s	529.063us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.310s	61.688us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.310s	61.688us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	10.470s	529.063us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.310s	61.688us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	10.470s	529.063us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.310s	61.688us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	4.710s	1.123ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.61942883042147826997523437480890871574582532091745131062338594737738004268672
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @  15137406 ps: (keymgr_csr_assert_fpv.sv:484) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @  15137406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_rw has 1 failures.

0.keymgr_csr_rw.59342879247696130425099404892182758427453789065535114505748580332314771855154
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @  20957863 ps: (keymgr_csr_assert_fpv.sv:478) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @  20957863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 0.keymgr_stress_all_with_rand_reset.93476993209352397347253877297475976337205479409441549141741018351535636873040
    Line 203, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1123293617 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1123293617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```