KMAC/UNMASKED Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: a2f86af

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	25.890s	1.758ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.850s	44.428us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.800s	178.193us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.930s	1.169ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.300s	772.507us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.040s	194.311us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.800s	178.193us	1	1	100.00
		kmac_csr_aliasing	4.300s	772.507us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.610s	15.084us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.880s	21.600us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	5.210m	14.822ms	1	1	100.00
V2	burst_write	kmac_burst_write	12.403m	36.380ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	18.659m	17.831ms	1	1	100.00
		kmac_test_vectors_sha3_256	28.200s	8.635ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.950s	2.308ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.681m	167.511ms	1	1	100.00
		kmac_test_vectors_shake_128	2.342m	9.991ms	1	1	100.00
		kmac_test_vectors_shake_256	4.829m	80.232ms	1	1	100.00
		kmac_test_vectors_kmac	2.760s	518.486us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.250s	58.161us	1	1	100.00
V2	sideload	kmac_sideload	3.380m	3.857ms	1	1	100.00
V2	app	kmac_app	1.641m	28.799ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	33.600s	10.124ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.213m	96.412ms	1	1	100.00
V2	error	kmac_error	4.259m	66.963ms	1	1	100.00
V2	key_error	kmac_key_error	7.250s	3.421ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.020s	665.558us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	6.280s	238.527us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	22.900s	4.115ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	34.100s	5.811ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.830s	133.753us	1	1	100.00
V2	stress_all	kmac_stress_all	14.078m	71.949ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.620s	24.284us	1	1	100.00
V2	alert_test	kmac_alert_test	1.650s	19.114us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.920s	387.002us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.920s	387.002us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.850s	44.428us	1	1	100.00
		kmac_csr_rw	1.800s	178.193us	1	1	100.00
		kmac_csr_aliasing	4.300s	772.507us	1	1	100.00
		kmac_same_csr_outstanding	2.030s	51.796us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.850s	44.428us	1	1	100.00
		kmac_csr_rw	1.800s	178.193us	1	1	100.00
		kmac_csr_aliasing	4.300s	772.507us	1	1	100.00
		kmac_same_csr_outstanding	2.030s	51.796us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.240s	129.072us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.240s	129.072us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.240s	129.072us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.240s	129.072us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.300s	189.351us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	20.590s	6.315ms	1	1	100.00
		kmac_tl_intg_err	3.830s	182.167us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.830s	182.167us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.830s	133.753us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	25.890s	1.758ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.380m	3.857ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.240s	129.072us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	20.590s	6.315ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	20.590s	6.315ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	20.590s	6.315ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	25.890s	1.758ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.830s	133.753us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	20.590s	6.315ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	34.320s	19.635ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	25.890s	1.758ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	34.310s	20.177ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.14705722392507400325560335135524885552313290743045860551459049355531274456653
      Line 130, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20176505898 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 20176505898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---