PATTGEN Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: `a2f86af`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	103.946us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	25.553us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	16.033us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	67.407us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	87.511us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	52.693us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	16.033us	1	1	100.00
		pattgen_csr_aliasing	4.000s	87.511us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	38.617m	600.000ms	0	1	0.00
V2	cnt_rollover	cnt_rollover	4.000s	172.452us	1	1	100.00
V2	error	pattgen_error	3.000s	76.886us	1	1	100.00
V2	stress_all	pattgen_stress_all	3.000s	29.466us	1	1	100.00
V2	alert_test	pattgen_alert_test	4.000s	16.540us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	20.369us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	501.210us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	501.210us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	25.553us	1	1	100.00
		pattgen_csr_rw	4.000s	16.033us	1	1	100.00
		pattgen_csr_aliasing	4.000s	87.511us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	53.082us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	25.553us	1	1	100.00
		pattgen_csr_rw	4.000s	16.033us	1	1	100.00
		pattgen_csr_aliasing	4.000s	87.511us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	53.082us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	156.348us	1	1	100.00
		pattgen_sec_cm	4.000s	260.420us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	156.348us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	20.000s	7.884ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	11.000s	10.267ms	0	1	0.00
		TOTAL			15	18	83.33

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pattgen_perf has 1 failures.
  - 0.pattgen_perf.7966032030078477001836695352529940534644163277778277247938040482902717853187
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 0.pattgen_inactive_level.85967758026468673065343682170504334447874813581777526987595539761773822735122
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10266547575 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x3df091d0, Comparison=CompareOpEq, exp_data=0x0, call_count=24)
  UVM_INFO @ 10266547575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.103032914720833752466779592613364958668830983433942897977269856529006802784684
Line 150, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2099892826 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2099923456 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2099923456 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/5
  UVM_INFO @ 2100131791 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]