ROM_CTRL/32KB Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: a2f86af

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.860s 823.283us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.980s 549.373us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.850s 555.843us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.690s 278.038us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.000s 374.552us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.950s 631.779us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.850s 555.843us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 374.552us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.110s 171.505us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.640s 559.951us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.720s 184.662us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 14.540s 4.034ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.390s 221.744us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.790s 533.751us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.410s 2.271ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.410s 2.271ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.980s 549.373us 1 1 100.00
rom_ctrl_csr_rw 5.850s 555.843us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 374.552us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.580s 145.512us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.980s 549.373us 1 1 100.00
rom_ctrl_csr_rw 5.850s 555.843us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 374.552us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.580s 145.512us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 59.730s 2.204ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 20.590s 861.564us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.402m 1.261ms 1 1 100.00
rom_ctrl_tl_intg_err 21.700s 857.779us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.402m 1.261ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.402m 1.261ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 59.730s 2.204ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 59.730s 2.204ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 59.730s 2.204ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 59.730s 2.204ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 59.730s 2.204ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.402m 1.261ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.402m 1.261ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.860s 823.283us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.860s 823.283us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.860s 823.283us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 21.700s 857.779us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 59.730s 2.204ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.390s 221.744us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 59.730s 2.204ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 59.730s 2.204ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 59.730s 2.204ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 20.590s 861.564us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.402m 1.261ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 4.151m 3.472ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00