ROM_CTRL/64KB Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: a2f86af

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.430s 298.959us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.960s 366.475us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 11.230s 295.606us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.750s 556.651us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.300s 408.294us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.200s 217.685us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 11.230s 295.606us 1 1 100.00
rom_ctrl_csr_aliasing 6.300s 408.294us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.160s 1.028ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.760s 706.417us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.460s 304.969us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 24.510s 746.681us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.240s 1.426ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.750s 788.898us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.910s 218.465us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.910s 218.465us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.960s 366.475us 1 1 100.00
rom_ctrl_csr_rw 11.230s 295.606us 1 1 100.00
rom_ctrl_csr_aliasing 6.300s 408.294us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.130s 1.537ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.960s 366.475us 1 1 100.00
rom_ctrl_csr_rw 11.230s 295.606us 1 1 100.00
rom_ctrl_csr_aliasing 6.300s 408.294us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.130s 1.537ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.002m 2.157ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 24.960s 1.059ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 4.647m 1.119ms 1 1 100.00
rom_ctrl_tl_intg_err 37.030s 492.620us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 4.647m 1.119ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 4.647m 1.119ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.002m 2.157ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.002m 2.157ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.002m 2.157ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.002m 2.157ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.002m 2.157ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 4.647m 1.119ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 4.647m 1.119ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.430s 298.959us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.430s 298.959us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.430s 298.959us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 37.030s 492.620us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.002m 2.157ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.240s 1.426ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.002m 2.157ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.002m 2.157ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.002m 2.157ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 24.960s 1.059ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 4.647m 1.119ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.987m 54.881ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00