RV_DM/USE_JTAG_INTERFACE Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: a2f86af

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 3.220s 981.047us 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.590s 185.357us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.440s 483.697us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 7.680s 9.050ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.350s 907.633us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 6.260s 13.994ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 2.140s 863.080us 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 21.610s 11.604ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 36.530s 73.005ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.240s 583.565us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 2.660s 672.742us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.020s 669.456us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.900s 193.558us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.910s 164.207us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.580s 753.038us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.930s 116.139us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 3.280s 1.265ms 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 2.240s 583.565us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.670s 197.014us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.050s 487.793us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.020s 669.456us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 2.000s 139.013us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.260s 431.682us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.790s 163.990us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 48.610s 6.397ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 18.550s 1.233ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.710s 20.554us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 18.550s 1.233ms 1 1 100.00
rv_dm_csr_rw 2.790s 163.990us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.530s 65.883us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.970s 120.810us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 3.220s 981.047us 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.460s 618.905us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.530s 243.201us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.730s 180.461us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.200s 1.154ms 1 1 100.00
V2 sba rv_dm_sba_tl_access 10.880s 4.684ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.480s 31.049us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 4.650s 1.705ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.810s 104.749us 0 1 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.000s 400.208us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 5.510s 2.217ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.730s 260.119us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.850s 129.317us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 9.400s 6.343ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.680s 54.796us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 2.120s 196.843us 1 1 100.00
V2 stress_all rv_dm_stress_all 5.860s 2.535ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.680s 108.968us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.600s 29.008us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.600s 29.008us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 18.550s 1.233ms 1 1 100.00
rv_dm_csr_hw_reset 2.260s 431.682us 1 1 100.00
rv_dm_csr_rw 2.790s 163.990us 1 1 100.00
rv_dm_same_csr_outstanding 4.440s 1.115ms 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 18.550s 1.233ms 1 1 100.00
rv_dm_csr_hw_reset 2.260s 431.682us 1 1 100.00
rv_dm_csr_rw 2.790s 163.990us 1 1 100.00
rv_dm_same_csr_outstanding 4.440s 1.115ms 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 2.560s 722.031us 1 1 100.00
rv_dm_tl_intg_err 8.250s 2.573ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 8.250s 2.573ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 5.510s 2.217ms 1 1 100.00
rv_dm_debug_disabled 1.870s 122.113us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 5.510s 2.217ms 1 1 100.00
rv_dm_debug_disabled 1.870s 122.113us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 3.220s 981.047us 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.830s 184.448us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.740s 159.045us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.740s 159.045us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.830s 184.448us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.790s 24.234us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.740s 20.526us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets