RV_TIMER Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: a2f86af

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.540s	31.501us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.560s	19.601us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.560s	22.943us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.160s	98.782us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.530s	66.033us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.110s	34.097us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.560s	22.943us	1	1	100.00
		rv_timer_csr_aliasing	1.530s	66.033us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	9.310s	19.490ms	1	1	100.00
V2	disabled	rv_timer_disabled	4.090s	2.456ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	7.349m	671.356ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	7.349m	671.356ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.490s	41.289us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.490s	23.424us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.500s	33.298us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.280s	146.696us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.280s	146.696us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.560s	19.601us	1	1	100.00
		rv_timer_csr_rw	1.560s	22.943us	1	1	100.00
		rv_timer_csr_aliasing	1.530s	66.033us	1	1	100.00
		rv_timer_same_csr_outstanding	1.670s	22.020us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.560s	19.601us	1	1	100.00
		rv_timer_csr_rw	1.560s	22.943us	1	1	100.00
		rv_timer_csr_aliasing	1.530s	66.033us	1	1	100.00
		rv_timer_same_csr_outstanding	1.670s	22.020us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.790s	1.000ms	1	1	100.00
		rv_timer_tl_intg_err	2.060s	394.228us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.060s	394.228us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	1.450s	36.642us	1	1	100.00
V3	max_value	rv_timer_max	1.410s	37.105us	1	1	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	24.030s	5.886ms	1	1	100.00
V3		TOTAL			3	3	100.00
		TOTAL			19	19	100.00