SPI_DEVICE/1R1W Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: a2f86af

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	18.980s	11.101ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.730s	25.853us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.410s	33.068us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	15.760s	354.604us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.120s	1.211ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.660s	647.919us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.410s	33.068us	1	1	100.00
		spi_device_csr_aliasing	15.120s	1.211ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.550s	41.440us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.250s	40.929us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.640s	34.527us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.540s	3.459us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.460s	6.233us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	5.920s	323.118us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	5.920s	323.118us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	9.270s	7.915ms	1	1	100.00
		spi_device_tpm_sts_read	1.760s	18.297us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	7.750s	6.137ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.600s	147.874us	1	1	100.00
		spi_device_flash_all	2.979m	85.830ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	6.760s	17.432ms	1	1	100.00
		spi_device_flash_all	2.979m	85.830ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	6.760s	17.432ms	1	1	100.00
		spi_device_flash_all	2.979m	85.830ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.979m	85.830ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.690s	1.171ms	1	1	100.00
		spi_device_flash_all	2.979m	85.830ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.690s	1.171ms	1	1	100.00
		spi_device_flash_all	2.979m	85.830ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.690s	1.171ms	1	1	100.00
		spi_device_flash_all	2.979m	85.830ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.690s	1.171ms	1	1	100.00
		spi_device_flash_all	2.979m	85.830ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.690s	1.171ms	1	1	100.00
		spi_device_flash_all	2.979m	85.830ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.850s	485.355us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	27.420s	99.466ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	27.420s	99.466ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	27.420s	99.466ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.910s	1.234ms	1	1	100.00
		spi_device_read_buffer_direct	5.170s	561.657us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	27.420s	99.466ms	1	1	100.00
		spi_device_flash_all	2.979m	85.830ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.979m	85.830ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.979m	85.830ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.780s	42.312us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.780s	42.312us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	18.980s	11.101ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.479m	37.060ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.100s	44.832us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.630s	38.018us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.710s	12.030us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.350s	571.322us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.350s	571.322us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.730s	25.853us	1	1	100.00
		spi_device_csr_rw	2.410s	33.068us	1	1	100.00
		spi_device_csr_aliasing	15.120s	1.211ms	1	1	100.00
		spi_device_same_csr_outstanding	2.260s	142.198us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.730s	25.853us	1	1	100.00
		spi_device_csr_rw	2.410s	33.068us	1	1	100.00
		spi_device_csr_aliasing	15.120s	1.211ms	1	1	100.00
		spi_device_same_csr_outstanding	2.260s	142.198us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.780s	51.396us	1	1	100.00
		spi_device_tl_intg_err	11.480s	1.108ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.480s	1.108ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	23.130s	3.742ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.16858310089584268077316900321665170146732268620398614243833601425965038775173
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2279485 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[71])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2279485 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2279485 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[967])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.81458829320521780256222537986097364038824459887967910700221149441631438472046
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3741142 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcef9f1 [110011101111100111110001] vs 0x0 [0])
        UVM_ERROR @   3834142 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x521e2b [10100100001111000101011] vs 0x0 [0])
        UVM_ERROR @   3900142 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf7da1a [111101111101101000011010] vs 0x0 [0])
        UVM_ERROR @   3985142 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1cd6a3 [111001101011010100011] vs 0x0 [0])
        UVM_ERROR @   3986142 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x50a0ab [10100001010000010101011] vs 0x0 [0])