SPI_DEVICE/2P Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: a2f86af

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.314m	45.437ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.030s	153.489us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.800s	87.930us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	21.950s	536.547us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.170s	357.642us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.560s	49.211us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.800s	87.930us	1	1	100.00
		spi_device_csr_aliasing	16.170s	357.642us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.620s	44.860us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.870s	61.083us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.690s	18.244us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.700s	119.699us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.500s	16.011us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.820s	40.522us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.820s	40.522us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.440s	900.942us	1	1	100.00
		spi_device_tpm_sts_read	1.780s	105.599us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	23.440s	12.204ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.520s	2.280ms	1	1	100.00
		spi_device_flash_all	1.605m	85.844ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.790s	15.987ms	1	1	100.00
		spi_device_flash_all	1.605m	85.844ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.790s	15.987ms	1	1	100.00
		spi_device_flash_all	1.605m	85.844ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.605m	85.844ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.790s	230.968us	1	1	100.00
		spi_device_flash_all	1.605m	85.844ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.790s	230.968us	1	1	100.00
		spi_device_flash_all	1.605m	85.844ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.790s	230.968us	1	1	100.00
		spi_device_flash_all	1.605m	85.844ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.790s	230.968us	1	1	100.00
		spi_device_flash_all	1.605m	85.844ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.790s	230.968us	1	1	100.00
		spi_device_flash_all	1.605m	85.844ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	14.870s	11.758ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	3.940s	330.686us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.940s	330.686us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.940s	330.686us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.370s	1.498ms	1	1	100.00
		spi_device_read_buffer_direct	3.540s	89.614us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.940s	330.686us	1	1	100.00
		spi_device_flash_all	1.605m	85.844ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.605m	85.844ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.605m	85.844ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.700s	93.482us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.700s	93.482us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.314m	45.437ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	45.620s	5.377ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.690s	328.364us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.540s	12.312us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.560s	14.081us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.240s	589.104us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.240s	589.104us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.030s	153.489us	1	1	100.00
		spi_device_csr_rw	2.800s	87.930us	1	1	100.00
		spi_device_csr_aliasing	16.170s	357.642us	1	1	100.00
		spi_device_same_csr_outstanding	2.900s	44.299us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.030s	153.489us	1	1	100.00
		spi_device_csr_rw	2.800s	87.930us	1	1	100.00
		spi_device_csr_aliasing	16.170s	357.642us	1	1	100.00
		spi_device_same_csr_outstanding	2.900s	44.299us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.940s	203.662us	1	1	100.00
		spi_device_tl_intg_err	14.950s	1.007ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	14.950s	1.007ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	49.140s	21.872ms	1	1	100.00
		TOTAL			33	33	100.00