SRAM_CTRL/RET Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: a2f86af

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	12.080s	1.878ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.620s	24.214us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.530s	62.263us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.390s	44.870us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.670s	12.639us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.020s	115.547us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.530s	62.263us	1	1	100.00
		sram_ctrl_csr_aliasing	1.670s	12.639us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.440s	949.348us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.560s	180.455us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	10.900m	8.641ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.400m	7.283ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	27.150s	609.088us	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.912m	10.585ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.320s	93.721us	1	1	100.00
V2	executable	sram_ctrl_executable	3.212m	23.633ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.750s	460.794us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.863m	199.211ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	4.730s	117.727us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	7.730s	159.071us	1	1	100.00
		sram_ctrl_throughput_w_readback	2.260s	93.952us	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.614m	9.920ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.640s	84.114us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	26.765m	12.049ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.570s	14.343us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.620s	110.835us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.620s	110.835us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.620s	24.214us	1	1	100.00
		sram_ctrl_csr_rw	1.530s	62.263us	1	1	100.00
		sram_ctrl_csr_aliasing	1.670s	12.639us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.560s	25.506us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.620s	24.214us	1	1	100.00
		sram_ctrl_csr_rw	1.530s	62.263us	1	1	100.00
		sram_ctrl_csr_aliasing	1.670s	12.639us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.560s	25.506us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.380s	460.126us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.590s	17.161us	0	1	0.00
		sram_ctrl_tl_intg_err	2.720s	735.849us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.590s	17.161us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.720s	735.849us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.614m	9.920ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.614m	9.920ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.530s	62.263us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.212m	23.633ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.212m	23.633ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.212m	23.633ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.320s	93.721us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.980s	439.570us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.380s	460.126us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.820s	251.314us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	12.080s	1.878ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	12.080s	1.878ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.212m	23.633ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.590s	17.161us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.320s	93.721us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.590s	17.161us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.590s	17.161us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	12.080s	1.878ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.590s	17.161us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	13.870s	328.899us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.45487775691328298253356876521101769786370103754607174501184634006967593136582
      Line 97, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @  17161178 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @  17161178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---