SYSRST_CTRL Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: a2f86af

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 2.700s 2.133ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 4.250s 2.459ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 2.350s 2.436ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.870s 2.614ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 2.520s 6.217ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 5.030s 2.035ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 1.251m 38.820ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 10.060s 3.097ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.600s 2.235ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 5.030s 2.035ms 1 1 100.00
sysrst_ctrl_csr_aliasing 10.060s 3.097ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 2.819m 88.656ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 4.466m 144.290ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 4.700s 2.863ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 2.070s 3.021ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 6.140s 2.511ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 3.800s 2.190ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 5.420s 2.780ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 6.290s 2.610ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 1.860s 4.801ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 19.190s 31.374ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 5.330s 11.282ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 4.100s 2.013ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 6.210s 2.011ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 4.760s 2.072ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 4.760s 2.072ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 2.520s 6.217ms 1 1 100.00
sysrst_ctrl_csr_rw 5.030s 2.035ms 1 1 100.00
sysrst_ctrl_csr_aliasing 10.060s 3.097ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.050s 4.999ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 2.520s 6.217ms 1 1 100.00
sysrst_ctrl_csr_rw 5.030s 2.035ms 1 1 100.00
sysrst_ctrl_csr_aliasing 10.060s 3.097ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.050s 4.999ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 1.507m 42.010ms 1 1 100.00
sysrst_ctrl_tl_intg_err 44.700s 22.233ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 44.700s 22.233ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 1.230m 1.654s 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00