UART Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: a2f86af

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.850s	306.652us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.430s	43.273us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.610s	24.180us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.930s	1.045ms	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.640s	131.953us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.780s	111.444us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.610s	24.180us	1	1	100.00
		uart_csr_aliasing	1.640s	131.953us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	29.930s	90.796ms	1	1	100.00
V2	parity	uart_smoke	1.850s	306.652us	1	1	100.00
		uart_tx_rx	29.930s	90.796ms	1	1	100.00
V2	parity_error	uart_intr	3.920s	18.978ms	1	1	100.00
		uart_rx_parity_err	1.950m	170.331ms	1	1	100.00
V2	watermark	uart_tx_rx	29.930s	90.796ms	1	1	100.00
		uart_intr	3.920s	18.978ms	1	1	100.00
V2	fifo_full	uart_fifo_full	49.310s	141.880ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	17.810s	24.381ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	27.560s	52.277ms	1	1	100.00
V2	rx_frame_err	uart_intr	3.920s	18.978ms	1	1	100.00
V2	rx_break_err	uart_intr	3.920s	18.978ms	1	1	100.00
V2	rx_timeout	uart_intr	3.920s	18.978ms	1	1	100.00
V2	perf	uart_perf	6.263m	10.124ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.410s	1.505ms	1	1	100.00
V2	line_loopback	uart_loopback	2.410s	1.505ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	11.420s	22.547ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	39.600s	35.943ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.780s	7.823ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	3.980s	5.453ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.472m	155.620ms	1	1	100.00
V2	stress_all	uart_stress_all	22.089m	337.838ms	1	1	100.00
V2	alert_test	uart_alert_test	1.550s	11.987us	1	1	100.00
V2	intr_test	uart_intr_test	1.480s	17.220us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.090s	466.281us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.090s	466.281us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.430s	43.273us	1	1	100.00
		uart_csr_rw	1.610s	24.180us	1	1	100.00
		uart_csr_aliasing	1.640s	131.953us	1	1	100.00
		uart_same_csr_outstanding	1.540s	20.845us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.430s	43.273us	1	1	100.00
		uart_csr_rw	1.610s	24.180us	1	1	100.00
		uart_csr_aliasing	1.640s	131.953us	1	1	100.00
		uart_same_csr_outstanding	1.540s	20.845us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	2.030s	67.534us	1	1	100.00
		uart_tl_intg_err	1.880s	103.332us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.880s	103.332us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	10.540s	8.999ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00