CHIP Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: `a2f86af`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.999m	2.931ms	1	1	100.00
		chip_sw_example_rom	1.191m	2.718ms	1	1	100.00
		chip_sw_example_manufacturer	1.807m	2.852ms	1	1	100.00
		chip_sw_example_concurrency	1.838m	2.697ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.352m	6.641ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.751m	6.181ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.419m	3.504ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.091h	37.203ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	59.750s	2.260ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.091h	37.203ms	1	1	100.00
		chip_csr_rw	5.751m	6.181ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	4.870s	42.445us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	3.534m	3.572ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	3.534m	3.572ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	3.534m	3.572ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.963m	3.942ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.963m	3.942ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.285m	4.011ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.914m	3.894ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.374m	4.407ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	5.424m	3.678ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	28.106m	13.454ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	8.766m	8.025ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.789m	4.754ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.789m	4.754ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.274m	2.755ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.238m	5.601ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.995m	3.317ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.389m	2.535ms	1	1	100.00
		chip_tap_straps_testunlock0	3.750m	4.710ms	1	1	100.00
		chip_tap_straps_rma	4.595m	4.584ms	1	1	100.00
		chip_tap_straps_prod	6.494m	7.286ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.590m	3.202ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.703m	9.797ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.849m	5.047ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.849m	5.047ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.160m	7.629ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	33.702m	22.241ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.361m	3.833ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.380m	6.015ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.772m	18.243ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.556m	3.109ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	13.014m	8.027ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.498m	3.307ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.873m	10.056ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.565m	3.395ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.104m	4.053ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.001m	2.277ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.242m	2.889ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.879m	5.861ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.764m	5.570ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.056m	2.387ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.764m	5.570ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.446m	2.977ms	1	1	100.00
		chip_sw_aes_smoketest	2.178m	3.542ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.119m	2.686ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.339m	2.700ms	1	1	100.00
		chip_sw_csrng_smoketest	2.341m	2.528ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.212m	3.295ms	1	1	100.00
		chip_sw_gpio_smoketest	3.498m	3.084ms	1	1	100.00
		chip_sw_hmac_smoketest	3.161m	2.833ms	1	1	100.00
		chip_sw_kmac_smoketest	3.437m	2.943ms	1	1	100.00
		chip_sw_otbn_smoketest	10.515m	6.324ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.439m	6.784ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.396m	6.153ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.016m	2.792ms	1	1	100.00
		chip_sw_rv_timer_smoketest	1.779m	2.858ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.294m	3.087ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.998m	2.350ms	1	1	100.00
		chip_sw_uart_smoketest	2.381m	3.110ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.791m	3.296ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.781m	4.473ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.012h	60.816ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	38.784m	14.704ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.469m	5.712ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.538m	2.836ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.243m	3.685ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.697h	53.730ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.896h	55.365ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	43.620s	2.666ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	43.620s	2.666ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.091h	37.203ms	1	1	100.00
		chip_same_csr_outstanding	46.510m	31.491ms	1	1	100.00
		chip_csr_hw_reset	3.352m	6.641ms	1	1	100.00
		chip_csr_rw	5.751m	6.181ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.091h	37.203ms	1	1	100.00
		chip_same_csr_outstanding	46.510m	31.491ms	1	1	100.00
		chip_csr_hw_reset	3.352m	6.641ms	1	1	100.00
		chip_csr_rw	5.751m	6.181ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	23.940s	1.039ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.470s	54.250us	1	1	100.00
		xbar_smoke_large_delays	41.140s	6.759ms	1	1	100.00
		xbar_smoke_slow_rsp	46.270s	4.976ms	1	1	100.00
		xbar_random_zero_delays	13.460s	235.302us	1	1	100.00
		xbar_random_large_delays	2.448m	24.814ms	1	1	100.00
		xbar_random_slow_rsp	2.446m	16.684ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	32.160s	995.677us	1	1	100.00
		xbar_error_and_unmapped_addr	16.640s	362.521us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	33.410s	1.521ms	1	1	100.00
		xbar_error_and_unmapped_addr	16.640s	362.521us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	7.470s	53.918us	1	1	100.00
		xbar_access_same_device_slow_rsp	11.930m	83.840ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	26.960s	1.446ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.828m	3.630ms	1	1	100.00
		xbar_stress_all_with_error	3.968m	11.804ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	7.701m	14.992ms	1	1	100.00
		xbar_stress_all_with_reset_error	21.980s	74.593us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	38.784m	14.704ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	32.743m	26.471ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.001m	15.714ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	29.450m	10.699ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	38.786m	15.800ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.369m	16.077ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.428m	15.384ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	37.727m	15.033ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	17.170s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.370s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.260s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.730s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.930s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.840s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.000s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.030s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.100s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	15.900s	10.140us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.100s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	15.330s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	24.170s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	15.550s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	15.320s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	15.490s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	15.650s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	15.380s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.170s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.700s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.220s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.120s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.700s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.070s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.500s	10.140us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.361m	11.518ms	1	1	100.00
		rom_e2e_asm_init_dev	36.486m	15.901ms	1	1	100.00
		rom_e2e_asm_init_prod	36.813m	15.873ms	1	1	100.00
		rom_e2e_asm_init_prod_end	36.545m	15.610ms	1	1	100.00
		rom_e2e_asm_init_rma	34.329m	14.157ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.012m	15.115ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.155m	14.872ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	34.951m	15.591ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.309m	15.463ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.982m	34.570ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.982m	34.570ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.875m	2.600ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.556m	3.109ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.186m	2.680ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.258m	2.599ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	24.125m	12.256ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.600m	3.725ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	3.899m	4.417ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.645m	6.250ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	7.892m	5.448ms	1	1	100.00
		chip_plic_all_irqs_10	3.659m	3.507ms	1	1	100.00
		chip_plic_all_irqs_20	5.244m	4.109ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.983m	2.835ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	18.025m	13.782ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.885m	4.799ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.578m	2.663ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.312m	12.388ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.700m	7.794ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.278m	6.904ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.982m	7.480ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.200h	256.533ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.413m	4.158ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.439m	6.784ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.413m	4.158ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.825m	9.724ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.825m	9.724ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.610m	6.763ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.617m	6.354ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.817m	5.408ms	1	1	100.00
		chip_sw_aes_idle	2.258m	2.599ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.018m	3.197ms	1	1	100.00
		chip_sw_kmac_idle	2.544m	2.339ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.859m	4.305ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.580m	4.682ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.973m	4.714ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	2.740m	3.635ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.901m	9.357ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.282m	3.713ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	4.962m	4.289ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.325m	4.242ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.965m	4.810ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.886m	3.864ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.080m	4.177ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.160m	7.629ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.622m	5.331ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.325m	4.242ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.965m	4.810ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.361m	3.833ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.380m	6.015ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.772m	18.243ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.556m	3.109ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	13.014m	8.027ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.498m	3.307ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.873m	10.056ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.565m	3.395ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.104m	4.053ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.001m	2.277ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.873m	3.328ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.122m	4.650ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.359m	7.265ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	46.886m	24.427ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.352m	3.062ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.567m	3.339ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.456m	7.871ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.682m	2.859ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.889m	4.254ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	17.013m	20.128ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	32.254m	18.188ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.160m	7.629ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.141m	4.285ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.580m	3.391ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.645m	6.250ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	16.700m	7.794ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	10.218m	5.884ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.882m	3.127ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.295m	5.372ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.962m	2.624ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	27.687m	10.958ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.802m	2.556ms	1	1	100.00
		chip_sw_edn_entropy_reqs	13.603m	6.732ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.802m	2.556ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	10.218m	5.884ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.343m	2.342ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	16.977m	16.079ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.739m	5.411ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.380m	6.015ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.825m	3.545ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.361m	3.833ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	53.340m	43.380ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	16.977m	16.079ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.607m	3.438ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	21.468m	11.164ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.483m	4.568ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	53.340m	43.380ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.483m	4.568ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.483m	4.568ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.483m	4.568ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.483m	4.568ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.645m	6.250ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.106m	3.368ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.802m	5.539ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.526m	6.446ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.526m	6.446ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	1.950m	2.630ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.498m	3.307ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.018m	3.197ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.929m	3.615ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.885m	4.054ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.324m	4.971ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.319m	4.297ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.880m	4.667ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.289m	3.939ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	21.468m	11.164ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.873m	10.056ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	26.837m	13.208ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	24.125m	12.256ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	31.037m	11.362ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.809m	2.118ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.454m	3.441ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.565m	3.395ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	21.468m	11.164ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	7.526m	10.209ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.247m	3.240ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	25.188m	11.282ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.544m	2.339ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	3.899m	4.417ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.389m	2.535ms	1	1	100.00
		chip_tap_straps_rma	4.595m	4.584ms	1	1	100.00
		chip_tap_straps_prod	6.494m	7.286ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.358m	2.664ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	7.526m	10.209ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	7.526m	10.209ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	7.526m	10.209ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	20.087m	11.397ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.483m	4.568ms	1	1	100.00
		chip_sw_flash_rma_unlocked	53.340m	43.380ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.879m	3.040ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	10.147m	7.068ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.480m	8.316ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.885m	7.187ms	1	1	100.00
		chip_sw_lc_ctrl_transition	7.526m	10.209ms	1	1	100.00
		chip_sw_keymgr_key_derivation	21.468m	11.164ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.847m	9.012ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.701m	10.415ms	1	1	100.00
		chip_prim_tl_access	1.106m	3.368ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.622m	5.331ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.282m	3.713ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	4.962m	4.289ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.325m	4.242ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.965m	4.810ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.886m	3.864ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.080m	4.177ms	1	1	100.00
		chip_tap_straps_dev	1.389m	2.535ms	1	1	100.00
		chip_tap_straps_rma	4.595m	4.584ms	1	1	100.00
		chip_tap_straps_prod	6.494m	7.286ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.232m	10.492ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	1.984m	2.599ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.285m	4.048ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.601m	3.186ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.711m	3.994ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.920m	26.882ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.232m	10.492ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.062h	47.926ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.043h	50.536ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.944m	9.098ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	59.569m	46.735ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	21.920m	26.882ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	52.820s	2.257ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.091m	2.960ms	1	1	100.00
		rom_volatile_raw_unlock	1.047m	2.864ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	50.634m	16.223ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.772m	18.243ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.817m	5.408ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.817m	5.408ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.817m	5.408ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	3.948m	3.226ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	7.526m	10.209ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	16.977m	16.079ms	1	1	100.00
		chip_sw_otbn_mem_scramble	3.948m	3.226ms	1	1	100.00
		chip_sw_keymgr_key_derivation	21.468m	11.164ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.583m	4.420ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.831m	1.955ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	16.977m	16.079ms	1	1	100.00
		chip_sw_otbn_mem_scramble	3.948m	3.226ms	1	1	100.00
		chip_sw_keymgr_key_derivation	21.468m	11.164ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.583m	4.420ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.831m	1.955ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	7.526m	10.209ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.425m	5.602ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.358m	2.664ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.879m	3.040ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	10.147m	7.068ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.480m	8.316ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.885m	7.187ms	1	1	100.00
		chip_sw_lc_ctrl_transition	7.526m	10.209ms	1	1	100.00
		chip_prim_tl_access	1.106m	3.368ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.106m	3.368ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.144m	9.086ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.480m	7.370ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	14.904m	25.690ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.537m	7.849ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.492m	9.839ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.451m	5.088ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.235m	23.190ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.017m	17.341ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.825m	9.724ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.062m	10.032ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.921m	5.622ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.480m	7.370ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.375m	5.001ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	25.632m	23.446ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.139m	7.710ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.521m	5.827ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	27.489m	24.682ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.874m	8.924ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.155m	10.371ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	28.346m	27.142ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.220m	3.010ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.645m	6.250ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.847m	9.012ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.847m	9.012ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.155m	10.371ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	27.489m	24.682ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.921m	5.622ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.439m	6.784ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.610m	4.732ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.527m	4.796ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	2.657m	4.594ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	18.025m	13.782ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.281m	2.600ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.645m	6.250ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.278m	6.904ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.389m	5.153ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.625m	4.310ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.104m	2.658ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.831m	1.955ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.527m	4.796ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.527m	4.796ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	11.975m	10.919ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.640m	14.119ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.610m	4.732ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.836m	5.470ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.290m	6.456ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	4.595m	4.584ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.232m	10.492ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	7.892m	5.448ms	1	1	100.00
		chip_plic_all_irqs_10	3.659m	3.507ms	1	1	100.00
		chip_plic_all_irqs_20	5.244m	4.109ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.295m	2.158ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.336m	3.654ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	38.784m	14.704ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.329m	6.691ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.295m	2.705ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.782m	3.903ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.042m	3.115ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.583m	4.420ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.104m	4.053ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.279m	7.585ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.839m	6.023ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.701m	10.415ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.645m	6.250ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.849m	5.047ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.874m	8.924ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	15.935m	20.980ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.516m	2.857ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.328m	3.828ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.190m	4.268ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	15.935m	20.980ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	15.935m	20.980ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	12.013m	10.946ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	12.013m	10.946ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.205m	5.946ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.982m	34.570ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.300m	3.015ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.298m	3.362ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.535m	3.610ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.996m	4.526ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.779m	8.275ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.287h	32.053ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.107m	11.972ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	1.730m	2.201ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.877m	2.706ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.228m	2.432ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.357h	71.749ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.825m	3.180ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.555m	11.359ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.321m	11.740ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.543m	11.435ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.489m	3.373ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.167m	4.555ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.905m	5.347ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.659s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.619m	5.240ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.816m	2.729ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	9.181m	4.327ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	22.807m	10.638ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.171m	2.720ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.800m	4.997ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.073m	2.419ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.756m	5.534ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.307m	4.518ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.082m	4.021ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.155m	10.371ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.555m	11.359ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.321m	11.740ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.543m	11.435ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.427m	5.532ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.645m	6.250ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.387h	37.858ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.387h	37.858ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.509m	3.117ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.963m	3.942ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	48.137m	19.177ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.631m	2.629ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.353m	5.664ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.917m	3.212ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.172m	3.127ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.787m	4.078ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.638s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.531m	3.357ms	1	1	100.00
		TOTAL			284	325	87.38

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.59629697859415810706978448504721209739735149434486898335254124219006584554288
    Line 630, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.52686617831958076792990731025839660266440175758111153703047047409823413656975
    Line 677, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.106255431100715791221125231753259833053053833446340632886182464735344356246174
    Line 752, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.88933087885296576053261150066938699829208838680324506739586850209289702245359
    Line 742, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.109799687603582727291749387443778864851839617742651941051590743353617625421325
    Line 750, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.73905145143672551469572053877387837186736774278056035953341872225455217329428
    Line 663, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.68206130717937622457201346418043839744455462449266359344978664653596113198897
    Line 664, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.110392931972397782966023265776220690968096322861196241402117280641647234817599
    Line 583, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.48827887845059570241093204895769382128675862587654674540361151767552193059268
    Line 655, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.5494058425504958518131078669396705703259035077921197084474222327475959193882
    Line 638, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.17293437749051016350825781984432505636195076226872351179421892824882723566537
    Line 760, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.30834126174831057324915854695004132673799993347543532683935703345997656278045
    Line 725, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.40178518177841569771285242703465486220805362259658774328118743540189454252684
    Line 658, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.18435857999290959052678583148607645400731236067734660757754106237106853684688
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.161s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.16403076946094028098354633847362226702189384236519380128779403835823878897580
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 2.536s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.109929342505144340533194816067542057923909676783134774553748541526244606301342
    Line 961, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.52679484772539963925911807141291864725297177722623003973283889836747750053491
    Line 788, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.87540954077106466157236678051940928094063082548154467897035762883041535973051
    Line 876, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.45927025627433254889631474823034012004333210561283454686790531540279480883590
    Line 661, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.68358658829836145424213041917083533910616064700112005674312524180369091284787
    Line 434, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2704.678230 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2704.678230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@91483) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.24977016923424525360065557852791818434960469568911728544387665982333296249889
Line 464, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4795.987324 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@91483) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4795.987324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.21309752709624644649482201537646276125219248702157138602982487618364933872301
    Line 433, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 10945.928768 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 10945.928768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.17247299142499247075837689571464833717858247329986719788713883053637554200156
    Line 431, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34569.511534 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34569.511534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.97744880967818494590781711709184851406661554733798311480586265205957688237596
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3725.045706 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 3725.045706 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.24909083782287618081260358748192777824057859363101419553772971630056785961493
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2663.118730 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2663.118730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.16880375091731620691171041393797646693786289518862427863063466932585330837349
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 3127.151303 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 3127.151303 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35149) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.88663619881850481549824565658363254231905143294847321120402754953345750813976
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2666.084290 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35149) { a_addr: 'h107a8  a_data: 'h736c5192  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2f  a_opcode: 'h4  a_user: 'h1a563  d_param: 'h0  d_source: 'h2f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2666.084290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.39087472502551532614706880737233766488496160585493910912541440164375173384312
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2431.548646 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2431.548646 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.103261821110947116011328206722581878499247048139903017744379575238454085230480
    Line 424, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2836.150000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2836.150000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.1194404945380465055822056963167580791695438203775440214004605313781190744107
    Line 440, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3685.167000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3685.167000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.62400734915894712500514547627299261623104765773258546240976724282752267271381
    Line 458, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 22241.262902 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 22241.262902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.26887072311452932591864485893869643758741860387953839116478013169111622216189
    Line 490, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3179.971171 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3179.971171 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.14406831207791719177287411648005560038051575216981012040456511603632192319697
    Line 797, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.35967922155574246825268617799019314721501063838154922412088192439059659327698
    Line 862, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31999) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.60874210535789594394557887282385936153858878380152660639185914603409369892229
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2259.781292 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31999) { a_addr: 'h104f0  a_data: 'h34c9f26a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h7  a_opcode: 'h4  a_user: 'h1b1fa  d_param: 'h0  d_source: 'h7  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2259.781292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---