ADC_CTRL Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	11.130s	5.721ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.380s	1.108ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.890s	344.158us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	35.240s	26.480ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.420s	954.318us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.210s	346.787us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.890s	344.158us	1	1	100.00
		adc_ctrl_csr_aliasing	2.420s	954.318us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	1.375m	317.919ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1.084m	166.553ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	12.556m	483.899ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.244m	163.860ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	10.321m	386.608ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	52.660s	597.901ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	2.182m	161.864ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.046m	2.000s	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.290s	3.645ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	14.670s	28.901ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	45.190s	100.374ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	4.532m	166.424ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.180s	382.043us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.500s	482.341us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.250s	577.144us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.250s	577.144us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.380s	1.108ms	1	1	100.00
		adc_ctrl_csr_rw	1.890s	344.158us	1	1	100.00
		adc_ctrl_csr_aliasing	2.420s	954.318us	1	1	100.00
		adc_ctrl_same_csr_outstanding	6.430s	2.029ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.380s	1.108ms	1	1	100.00
		adc_ctrl_csr_rw	1.890s	344.158us	1	1	100.00
		adc_ctrl_csr_aliasing	2.420s	954.318us	1	1	100.00
		adc_ctrl_same_csr_outstanding	6.430s	2.029ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	3.180s	5.186ms	1	1	100.00
		adc_ctrl_tl_intg_err	4.320s	4.351ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	4.320s	4.351ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.670s	2.608ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.25352950515026574428523404020568204274405806457920558725774021313394601865242
      Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---