EDN Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.780s 118.852us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.740s 34.023us 1 1 100.00
V1 csr_rw edn_csr_rw 1.720s 12.116us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.040s 98.529us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.970s 79.842us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.850s 21.928us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.720s 12.116us 1 1 100.00
edn_csr_aliasing 1.970s 79.842us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.150s 51.355us 1 1 100.00
V2 csrng_commands edn_genbits 2.150s 51.355us 1 1 100.00
V2 genbits edn_genbits 2.150s 51.355us 1 1 100.00
V2 interrupts edn_intr 1.770s 37.706us 1 1 100.00
V2 alerts edn_alert 1.960s 222.417us 1 1 100.00
V2 errs edn_err 1.580s 32.953us 1 1 100.00
V2 disable edn_disable 1.740s 13.524us 1 1 100.00
edn_disable_auto_req_mode 1.940s 48.756us 1 1 100.00
V2 stress_all edn_stress_all 2.560s 101.354us 1 1 100.00
V2 intr_test edn_intr_test 1.760s 15.432us 1 1 100.00
V2 alert_test edn_alert_test 1.920s 24.044us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.940s 542.641us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.940s 542.641us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.740s 34.023us 1 1 100.00
edn_csr_rw 1.720s 12.116us 1 1 100.00
edn_csr_aliasing 1.970s 79.842us 1 1 100.00
edn_same_csr_outstanding 2.040s 187.633us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.740s 34.023us 1 1 100.00
edn_csr_rw 1.720s 12.116us 1 1 100.00
edn_csr_aliasing 1.970s 79.842us 1 1 100.00
edn_same_csr_outstanding 2.040s 187.633us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 5.090s 689.483us 1 1 100.00
edn_tl_intg_err 2.810s 898.408us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.720s 15.569us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.960s 222.417us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 5.090s 689.483us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 5.090s 689.483us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 5.090s 689.483us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 5.090s 689.483us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.960s 222.417us 1 1 100.00
edn_sec_cm 5.090s 689.483us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.960s 222.417us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.810s 898.408us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets