HMAC Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 3.860s 286.059us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.680s 39.379us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.580s 18.427us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.770s 862.968us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.270s 311.763us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.801m 104.097ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.580s 18.427us 1 1 100.00
hmac_csr_aliasing 5.270s 311.763us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 49.730s 1.287ms 1 1 100.00
V2 back_pressure hmac_back_pressure 37.450s 2.801ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.932m 5.133ms 1 1 100.00
hmac_test_sha384_vectors 6.033m 44.229ms 1 1 100.00
hmac_test_sha512_vectors 7.812m 97.071ms 1 1 100.00
hmac_test_hmac256_vectors 10.730s 1.225ms 1 1 100.00
hmac_test_hmac384_vectors 9.770s 309.611us 1 1 100.00
hmac_test_hmac512_vectors 10.720s 315.327us 1 1 100.00
V2 burst_wr hmac_burst_wr 11.120s 499.282us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 4.154m 14.698ms 1 1 100.00
V2 error hmac_error 16.310s 2.570ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.301m 53.846ms 1 1 100.00
V2 save_and_restore hmac_smoke 3.860s 286.059us 1 1 100.00
hmac_long_msg 49.730s 1.287ms 1 1 100.00
hmac_back_pressure 37.450s 2.801ms 1 1 100.00
hmac_datapath_stress 4.154m 14.698ms 1 1 100.00
hmac_burst_wr 11.120s 499.282us 1 1 100.00
hmac_stress_all 1.480s 40.601us 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 3.860s 286.059us 1 1 100.00
hmac_long_msg 49.730s 1.287ms 1 1 100.00
hmac_back_pressure 37.450s 2.801ms 1 1 100.00
hmac_datapath_stress 4.154m 14.698ms 1 1 100.00
hmac_wipe_secret 1.301m 53.846ms 1 1 100.00
hmac_test_sha256_vectors 2.932m 5.133ms 1 1 100.00
hmac_test_sha384_vectors 6.033m 44.229ms 1 1 100.00
hmac_test_sha512_vectors 7.812m 97.071ms 1 1 100.00
hmac_test_hmac256_vectors 10.730s 1.225ms 1 1 100.00
hmac_test_hmac384_vectors 9.770s 309.611us 1 1 100.00
hmac_test_hmac512_vectors 10.720s 315.327us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 3.860s 286.059us 1 1 100.00
hmac_long_msg 49.730s 1.287ms 1 1 100.00
hmac_back_pressure 37.450s 2.801ms 1 1 100.00
hmac_datapath_stress 4.154m 14.698ms 1 1 100.00
hmac_burst_wr 11.120s 499.282us 1 1 100.00
hmac_error 16.310s 2.570ms 1 1 100.00
hmac_wipe_secret 1.301m 53.846ms 1 1 100.00
hmac_test_sha256_vectors 2.932m 5.133ms 1 1 100.00
hmac_test_sha384_vectors 6.033m 44.229ms 1 1 100.00
hmac_test_sha512_vectors 7.812m 97.071ms 1 1 100.00
hmac_test_hmac256_vectors 10.730s 1.225ms 1 1 100.00
hmac_test_hmac384_vectors 9.770s 309.611us 1 1 100.00
hmac_test_hmac512_vectors 10.720s 315.327us 1 1 100.00
hmac_stress_all 1.480s 40.601us 1 1 100.00
V2 stress_all hmac_stress_all 1.480s 40.601us 1 1 100.00
V2 alert_test hmac_alert_test 1.380s 38.760us 1 1 100.00
V2 intr_test hmac_intr_test 1.840s 64.412us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.240s 164.303us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.240s 164.303us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.680s 39.379us 1 1 100.00
hmac_csr_rw 1.580s 18.427us 1 1 100.00
hmac_csr_aliasing 5.270s 311.763us 1 1 100.00
hmac_same_csr_outstanding 2.020s 51.536us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.680s 39.379us 1 1 100.00
hmac_csr_rw 1.580s 18.427us 1 1 100.00
hmac_csr_aliasing 5.270s 311.763us 1 1 100.00
hmac_same_csr_outstanding 2.020s 51.536us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.610s 85.993us 1 1 100.00
hmac_tl_intg_err 2.540s 425.519us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.540s 425.519us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 3.860s 286.059us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.420s 135.412us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.615m 6.193ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.030s 95.568us 1 1 100.00
TOTAL 28 28 100.00