I2C Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	13.850s	4.899ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.300s	1.027ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.540s	27.658us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.620s	43.811us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.380s	354.642us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.910s	29.454us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.630s	38.460us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.620s	43.811us	1	1	100.00
		i2c_csr_aliasing	1.910s	29.454us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.760s	1.210ms	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	12.871m	50.371ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	1.276m	5.412ms	1	1	100.00
V2	host_override	i2c_host_override	1.590s	26.979us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	42.670s	6.887ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	22.370s	1.549ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.820s	134.874us	1	1	100.00
		i2c_host_fifo_fmt_empty	6.590s	807.278us	1	1	100.00
		i2c_host_fifo_reset_rx	4.650s	1.043ms	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	32.350s	7.366ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	6.900s	2.300ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.400s	122.942us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.730s	26.570ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	32.250s	33.011ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	2.860s	3.669ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	37.640s	4.975ms	1	1	100.00
		i2c_target_intr_smoke	4.220s	865.407us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.930s	172.910us	1	1	100.00
		i2c_target_fifo_reset_tx	1.820s	461.038us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	16.492m	65.046ms	1	1	100.00
		i2c_target_stress_rd	37.640s	4.975ms	1	1	100.00
		i2c_target_intr_stress_wr	5.900s	9.551ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.240s	5.053ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	38.390s	3.062ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.550s	784.182us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.990s	344.980us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.570s	2.813ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.740s	286.139us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.276m	5.412ms	1	1	100.00
		i2c_host_perf_precise	7.530s	778.728us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	6.900s	2.300ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	6.180s	562.284us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.100s	499.851us	1	1	100.00
		i2c_target_nack_acqfull_addr	3.010s	536.957us	1	1	100.00
		i2c_target_nack_txstretch	2.100s	146.165us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.620s	438.557us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.380s	2.063ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.530s	46.207us	1	1	100.00
V2	intr_test	i2c_intr_test	1.550s	20.061us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.490s	72.823us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.490s	72.823us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.540s	27.658us	1	1	100.00
		i2c_csr_rw	1.620s	43.811us	1	1	100.00
		i2c_csr_aliasing	1.910s	29.454us	1	1	100.00
		i2c_same_csr_outstanding	1.950s	122.564us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.540s	27.658us	1	1	100.00
		i2c_csr_rw	1.620s	43.811us	1	1	100.00
		i2c_csr_aliasing	1.910s	29.454us	1	1	100.00
		i2c_same_csr_outstanding	1.950s	122.564us	1	1	100.00
V2		TOTAL			38	38	100.00
V2S	tl_intg_err	i2c_tl_intg_err	1.910s	66.471us	1	1	100.00
		i2c_sec_cm	1.920s	152.504us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.910s	66.471us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	10.430s	1.094ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.580s	67.941us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	21.960s	13.195ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			47	50	94.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.102658814770091817803337412311022056263078650520402410664788466231965410434254
      Line 95, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1093683211 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1093683211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.75563755127594355698612766720131198952710373172461627559709117251644414114874
      Line 130, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13194509826 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 13194509826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.96330336219410874566080740158430473424587682380658552850047574056537150197193
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  67940596 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @  67940596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---