KEYMGR Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.490s	85.347us	1	1	100.00
V1	random	keymgr_random	4.920s	614.724us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.960s	134.433us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.830s	10.731us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	9.800s	1.786ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.150s	612.570us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.580s	30.003us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.830s	10.731us	0	1	0.00
		keymgr_csr_aliasing	7.150s	612.570us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	3.420s	57.925us	1	1	100.00
V2	sideload	keymgr_sideload	2.540s	88.076us	1	1	100.00
		keymgr_sideload_kmac	3.130s	215.068us	1	1	100.00
		keymgr_sideload_aes	3.090s	283.414us	1	1	100.00
		keymgr_sideload_otbn	15.600s	1.219ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.250s	240.598us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	5.050s	844.506us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.430s	57.775us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.530s	58.201us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.030s	64.522us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.800s	178.403us	1	1	100.00
V2	stress_all	keymgr_stress_all	22.930s	1.272ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.720s	130.463us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.910s	18.370us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.560s	159.995us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.560s	159.995us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.960s	134.433us	1	1	100.00
		keymgr_csr_rw	1.830s	10.731us	0	1	0.00
		keymgr_csr_aliasing	7.150s	612.570us	1	1	100.00
		keymgr_same_csr_outstanding	2.700s	89.973us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.960s	134.433us	1	1	100.00
		keymgr_csr_rw	1.830s	10.731us	0	1	0.00
		keymgr_csr_aliasing	7.150s	612.570us	1	1	100.00
		keymgr_same_csr_outstanding	2.700s	89.973us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	5.900s	632.888us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.900s	632.888us	1	1	100.00
		keymgr_tl_intg_err	7.400s	817.924us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.770s	207.614us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.770s	207.614us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.770s	207.614us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.770s	207.614us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.210s	239.173us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	5.900s	632.888us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.900s	632.888us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.400s	817.924us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.770s	207.614us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.420s	57.925us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.920s	614.724us	1	1	100.00
		keymgr_csr_rw	1.830s	10.731us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.920s	614.724us	1	1	100.00
		keymgr_csr_rw	1.830s	10.731us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.920s	614.724us	1	1	100.00
		keymgr_csr_rw	1.830s	10.731us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.050s	844.506us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.030s	64.522us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.030s	64.522us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.920s	614.724us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	4.330s	314.209us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.900s	632.888us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.900s	632.888us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.900s	632.888us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	4.930s	615.560us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.050s	844.506us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.900s	632.888us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.900s	632.888us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.900s	632.888us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	4.930s	615.560us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	4.930s	615.560us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.900s	632.888us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	4.930s	615.560us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.900s	632.888us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	4.930s	615.560us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	9.410s	321.222us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.81067766726949517536800801934418582343867547960027589156874283437893784782605
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
        UVM_ERROR @  10730823 ps: (keymgr_csr_assert_fpv.sv:430) [ASSERT FAILED] sealing_sw_binding_5_rd_A
        UVM_INFO @  10730823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---