KMAC/MASKED Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	50.730s	1.728ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.810s	23.391us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.690s	25.455us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	11.500s	427.718us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.580s	1.515ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.080s	40.595us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.690s	25.455us	1	1	100.00
		kmac_csr_aliasing	7.580s	1.515ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.490s	41.491us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.890s	16.269us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	3.273m	19.548ms	1	1	100.00
V2	burst_write	kmac_burst_write	21.168m	42.745ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.000s	6.810ms	1	1	100.00
		kmac_test_vectors_sha3_256	28.150s	4.667ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.550s	5.894ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.052m	125.414ms	1	1	100.00
		kmac_test_vectors_shake_128	26.113m	345.910ms	1	1	100.00
		kmac_test_vectors_shake_256	30.406m	362.155ms	1	1	100.00
		kmac_test_vectors_kmac	2.950s	311.446us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.700s	173.431us	1	1	100.00
V2	sideload	kmac_sideload	6.504m	64.136ms	1	1	100.00
V2	app	kmac_app	18.770s	1.455ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	8.760s	1.916ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	16.240s	1.303ms	1	1	100.00
V2	error	kmac_error	4.050m	11.601ms	1	1	100.00
V2	key_error	kmac_key_error	6.750s	1.744ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.650s	99.152us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	31.340s	1.309ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.010s	22.274us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	13.450s	15.776ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.580s	33.178us	1	1	100.00
V2	stress_all	kmac_stress_all	6.837m	9.220ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.720s	148.677us	1	1	100.00
V2	alert_test	kmac_alert_test	1.990s	15.228us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.820s	95.770us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.820s	95.770us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.810s	23.391us	1	1	100.00
		kmac_csr_rw	1.690s	25.455us	1	1	100.00
		kmac_csr_aliasing	7.580s	1.515ms	1	1	100.00
		kmac_same_csr_outstanding	2.060s	84.060us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.810s	23.391us	1	1	100.00
		kmac_csr_rw	1.690s	25.455us	1	1	100.00
		kmac_csr_aliasing	7.580s	1.515ms	1	1	100.00
		kmac_same_csr_outstanding	2.060s	84.060us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.310s	129.456us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.310s	129.456us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.310s	129.456us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.310s	129.456us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.740s	370.323us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.310m	27.224ms	1	1	100.00
		kmac_tl_intg_err	1.690s	42.309us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.690s	42.309us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.580s	33.178us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	50.730s	1.728ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.504m	64.136ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.310s	129.456us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.310m	27.224ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.310m	27.224ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.310m	27.224ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	50.730s	1.728ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.580s	33.178us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.310m	27.224ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	56.500s	4.993ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	50.730s	1.728ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	13.850s	663.581us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.18671615457521535897107107418591604708183849040585436033759873940680384951051
      Line 98, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 663580642 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 663580642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.42528507731802588597653655028970561047355714051381213342681470395107983509264
      Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
        UVM_ERROR @  42309181 ps: (kmac_csr_assert_fpv.sv:524) [ASSERT FAILED] prefix_4_rd_A
        UVM_INFO @  42309181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---