KMAC/UNMASKED Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	29.930s	2.148ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.780s	35.874us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.990s	51.213us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.010s	3.017ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.280s	609.870us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.320s	262.196us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.990s	51.213us	1	1	100.00
		kmac_csr_aliasing	4.280s	609.870us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.560s	13.359us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.060s	61.187us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	17.480m	88.710ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.684m	12.514ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	17.305m	134.958ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.060s	4.312ms	1	1	100.00
		kmac_test_vectors_sha3_384	16.226m	179.455ms	1	1	100.00
		kmac_test_vectors_sha3_512	8.802m	9.360ms	1	1	100.00
		kmac_test_vectors_shake_128	2.502m	24.643ms	1	1	100.00
		kmac_test_vectors_shake_256	16.786m	69.354ms	1	1	100.00
		kmac_test_vectors_kmac	2.980s	410.971us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.030s	237.596us	1	1	100.00
V2	sideload	kmac_sideload	3.839m	61.296ms	1	1	100.00
V2	app	kmac_app	1.193m	4.540ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	19.800s	1.277ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	10.760s	2.133ms	1	1	100.00
V2	error	kmac_error	3.943m	32.553ms	1	1	100.00
V2	key_error	kmac_key_error	9.860s	7.652ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.330s	110.401us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	16.590s	1.334ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	15.990s	4.352ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	43.910s	5.939ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.180s	57.272us	1	1	100.00
V2	stress_all	kmac_stress_all	11.296m	34.357ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.640s	107.727us	1	1	100.00
V2	alert_test	kmac_alert_test	1.730s	15.149us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.030s	175.987us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.030s	175.987us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.780s	35.874us	1	1	100.00
		kmac_csr_rw	1.990s	51.213us	1	1	100.00
		kmac_csr_aliasing	4.280s	609.870us	1	1	100.00
		kmac_same_csr_outstanding	2.980s	269.933us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.780s	35.874us	1	1	100.00
		kmac_csr_rw	1.990s	51.213us	1	1	100.00
		kmac_csr_aliasing	4.280s	609.870us	1	1	100.00
		kmac_same_csr_outstanding	2.980s	269.933us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.420s	76.911us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.420s	76.911us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.420s	76.911us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.420s	76.911us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.810s	11.271us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	41.320s	3.413ms	1	1	100.00
		kmac_tl_intg_err	3.300s	436.510us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.300s	436.510us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.180s	57.272us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	29.930s	2.148ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.839m	61.296ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.420s	76.911us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	41.320s	3.413ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	41.320s	3.413ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	41.320s	3.413ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	29.930s	2.148ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.180s	57.272us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	41.320s	3.413ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	14.880s	252.519us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	29.930s	2.148ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.249m	4.751ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.42730816419444576275527204214171648361268182068585724960984741736082668474803
      Line 223, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4751229777 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 4751229777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.93309875161584024546625084439018684805038844949012213682891245971117802663939
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
        UVM_ERROR @  11270876 ps: (kmac_csr_assert_fpv.sv:554) [ASSERT FAILED] prefix_9_rd_A
        UVM_INFO @  11270876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---