OTBN Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	39.364us	1	1	100.00
V1	single_binary	otbn_single	10.000s	31.390us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	48.501us	1	1	100.00
V1	csr_rw	otbn_csr_rw	7.000s	44.578us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	142.572us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	9.000s	28.997us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	150.937us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	44.578us	1	1	100.00
		otbn_csr_aliasing	9.000s	28.997us	1	1	100.00
V1	mem_walk	otbn_mem_walk	18.000s	1.204ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	13.000s	78.341us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	21.000s	132.896us	1	1	100.00
V2	multi_error	otbn_multi_err	50.000s	146.657us	1	1	100.00
V2	back_to_back	otbn_multi	51.000s	295.460us	1	1	100.00
V2	stress_all	otbn_stress_all	1.250m	293.887us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	24.859us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	39.530us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	8.000s	30.262us	1	1	100.00
V2	alert_test	otbn_alert_test	8.000s	28.854us	1	1	100.00
V2	intr_test	otbn_intr_test	7.000s	32.577us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	9.000s	59.271us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	9.000s	59.271us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	48.501us	1	1	100.00
		otbn_csr_rw	7.000s	44.578us	1	1	100.00
		otbn_csr_aliasing	9.000s	28.997us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	26.032us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	48.501us	1	1	100.00
		otbn_csr_rw	7.000s	44.578us	1	1	100.00
		otbn_csr_aliasing	9.000s	28.997us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	26.032us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	10.000s	52.127us	1	1	100.00
		otbn_dmem_err	10.000s	19.778us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	54.075us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	56.235us	1	1	100.00
		otbn_mac_bignum_acc_err	9.000s	53.764us	1	1	100.00
		otbn_urnd_err	8.000s	46.500us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	55.191us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	1.133m	10.001ms	0	1	0.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	42.534us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	14.000s	50.248us	0	1	0.00
		otbn_tl_intg_err	27.000s	125.889us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	59.000s	845.783us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	14.000s	50.248us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	14.000s	50.248us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	39.364us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	10.000s	19.778us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	52.127us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	27.000s	125.889us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	24.859us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	52.127us	1	1	100.00
		otbn_dmem_err	10.000s	19.778us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	39.530us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	55.191us	1	1	100.00
		otbn_sec_cm	14.000s	50.248us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	14.000s	50.248us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	10.000s	31.390us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	52.127us	1	1	100.00
		otbn_dmem_err	10.000s	19.778us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	39.530us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	55.191us	1	1	100.00
		otbn_sec_cm	14.000s	50.248us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	14.000s	50.248us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	24.859us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	52.127us	1	1	100.00
		otbn_dmem_err	10.000s	19.778us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	39.530us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	55.191us	1	1	100.00
		otbn_sec_cm	14.000s	50.248us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	14.000s	50.248us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	10.000s	31.390us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	25.579us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	12.000s	41.662us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.350m	608.363us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.350m	608.363us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	31.505us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	14.000s	50.248us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	14.000s	50.248us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	10.000s	187.863us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	14.000s	50.248us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	14.000s	50.248us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	17.000s	40.920us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	17.000s	40.920us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	8.000s	39.915us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	10.000s	31.390us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	10.000s	31.390us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	10.000s	31.390us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	51.000s	295.460us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	10.000s	31.390us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	10.000s	31.390us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	22.301us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	10.000s	31.390us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	14.000s	50.248us	0	1	0.00
V2S		TOTAL			17	20	85.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	4.417m	1.052ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	41	92.68

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.79308087707539924830029665941004907765689409800397035274837767842112118086649
      Line 113, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 39915001 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  39915001 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  39915001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_mem_gnt_acc_err_vseq.sv:41) [otbn_mem_gnt_acc_err_vseq] timeout occurred! has 1 failures:

  • Test otbn_mem_gnt_acc_err has 1 failures.

    • 0.otbn_mem_gnt_acc_err.104746648602093122915321971109523601492908279587478926487751981709263087478821
      Line 106, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest/run.log

        UVM_FATAL @ 10000968617 ps: (otbn_mem_gnt_acc_err_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.otbn_mem_gnt_acc_err_vseq] timeout occurred!
        UVM_INFO @ 10000968617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.30457487320971564911546044770259627927807116452707239621313876434396528289518
      Line 124, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 50247658 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 50247658 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  50247658 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  50247658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---