ROM_CTRL/64KB Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.690s 3.246ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 10.400s 7.077ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.020s 371.741us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.570s 1.029ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.720s 559.596us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.590s 1.538ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.020s 371.741us 1 1 100.00
rom_ctrl_csr_aliasing 6.720s 559.596us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.510s 1.071ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.000s 216.464us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.390s 306.066us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 16.840s 4.107ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.260s 1.064ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.760s 726.224us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.620s 288.399us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.620s 288.399us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 10.400s 7.077ms 1 1 100.00
rom_ctrl_csr_rw 6.020s 371.741us 1 1 100.00
rom_ctrl_csr_aliasing 6.720s 559.596us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.930s 397.045us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 10.400s 7.077ms 1 1 100.00
rom_ctrl_csr_rw 6.020s 371.741us 1 1 100.00
rom_ctrl_csr_aliasing 6.720s 559.596us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.930s 397.045us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.737m 20.736ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 20.240s 1.906ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 4.739m 990.532us 1 1 100.00
rom_ctrl_tl_intg_err 1.062m 3.634ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 4.739m 990.532us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 4.739m 990.532us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.737m 20.736ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.737m 20.736ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.737m 20.736ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.737m 20.736ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.737m 20.736ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 4.739m 990.532us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 4.739m 990.532us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.690s 3.246ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.690s 3.246ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.690s 3.246ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.062m 3.634ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.737m 20.736ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.260s 1.064ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.737m 20.736ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.737m 20.736ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.737m 20.736ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 20.240s 1.906ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 4.739m 990.532us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 40.330s 1.800ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00