RV_DM/USE_JTAG_INTERFACE Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 4.390s 2.992ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.050s 359.197us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.660s 490.556us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 36.130s 16.959ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.140s 347.285us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 3.330s 2.435ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 9.550s 7.208ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.820s 2.323ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 55.400s 28.929ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.410s 491.941us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 2.010s 246.935us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.910s 172.086us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.780s 163.835us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 2.020s 144.516us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 3.400s 1.062ms 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.890s 179.563us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 3.660s 982.134us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 2.410s 491.941us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.700s 97.210us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.990s 346.278us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.910s 172.086us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.860s 69.184us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.180s 231.920us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.150s 58.973us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 23.930s 4.938ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 43.320s 2.282ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 2.550s 127.435us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 43.320s 2.282ms 1 1 100.00
rv_dm_csr_rw 2.150s 58.973us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.900s 179.712us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.740s 29.845us 1 1 100.00
V1 TOTAL 27 27 100.00
V2 idcode rv_dm_smoke 4.390s 2.992ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.560s 318.288us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.230s 355.931us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 2.430s 230.441us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.600s 971.264us 1 1 100.00
V2 sba rv_dm_sba_tl_access 2.960s 3.289ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.730s 73.578us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 8.720s 5.043ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 8.010s 10.691ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.990s 260.409us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 11.420s 5.572ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.820s 673.479us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.710s 75.708us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 16.810s 10.654ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 1.630s 18.928us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.800s 168.121us 1 1 100.00
V2 stress_all rv_dm_stress_all 4.610s 1.767ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.840s 71.156us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.650s 48.019us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.650s 48.019us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 43.320s 2.282ms 1 1 100.00
rv_dm_csr_hw_reset 2.180s 231.920us 1 1 100.00
rv_dm_csr_rw 2.150s 58.973us 1 1 100.00
rv_dm_same_csr_outstanding 4.990s 573.008us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 43.320s 2.282ms 1 1 100.00
rv_dm_csr_hw_reset 2.180s 231.920us 1 1 100.00
rv_dm_csr_rw 2.150s 58.973us 1 1 100.00
rv_dm_same_csr_outstanding 4.990s 573.008us 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 4.160s 1.144ms 1 1 100.00
rv_dm_tl_intg_err 18.320s 7.711ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 18.320s 7.711ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 11.420s 5.572ms 1 1 100.00
rv_dm_debug_disabled 1.720s 46.072us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 11.420s 5.572ms 1 1 100.00
rv_dm_debug_disabled 1.720s 46.072us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 4.390s 2.992ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.750s 420.361us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.860s 188.525us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.860s 188.525us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.750s 420.361us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.640s 31.827us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.710s 48.037us 1 1 100.00
TOTAL 48 53 90.57

Failure Buckets