| V1 |
random |
rv_timer_random |
1.770s |
17.666us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
1.670s |
29.890us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
1.470s |
45.398us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
2.010s |
72.255us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
1.600s |
158.369us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
1.660s |
39.457us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
1.470s |
45.398us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.600s |
158.369us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
7.860s |
86.099ms |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
2.110s |
357.828us |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
3.951m |
247.042ms |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
3.951m |
247.042ms |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
4.730s |
12.066ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
1.390s |
38.835us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
1.570s |
75.227us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
2.790s |
126.768us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
2.790s |
126.768us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
1.670s |
29.890us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.470s |
45.398us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.600s |
158.369us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.650s |
192.632us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
1.670s |
29.890us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.470s |
45.398us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.600s |
158.369us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.650s |
192.632us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
1.680s |
71.654us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
2.040s |
143.599us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
2.040s |
143.599us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
1.420s |
15.751us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
1.580s |
11.703us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
43.640s |
23.943ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |