SPI_DEVICE/1R1W Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.228m	24.792ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.800s	66.860us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.800s	39.047us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.930s	750.268us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.770s	946.242us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.680s	501.080us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.800s	39.047us	1	1	100.00
		spi_device_csr_aliasing	16.770s	946.242us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.470s	19.181us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.990s	35.526us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.770s	140.926us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.560s	5.350us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.590s	5.888us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.180s	103.817us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.180s	103.817us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.950s	1.059ms	1	1	100.00
		spi_device_tpm_sts_read	1.590s	18.231us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	6.510s	5.234ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.210s	617.344us	1	1	100.00
		spi_device_flash_all	1.949m	197.167ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.670s	721.886us	1	1	100.00
		spi_device_flash_all	1.949m	197.167ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.670s	721.886us	1	1	100.00
		spi_device_flash_all	1.949m	197.167ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.949m	197.167ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.940s	1.499ms	1	1	100.00
		spi_device_flash_all	1.949m	197.167ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.940s	1.499ms	1	1	100.00
		spi_device_flash_all	1.949m	197.167ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.940s	1.499ms	1	1	100.00
		spi_device_flash_all	1.949m	197.167ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.940s	1.499ms	1	1	100.00
		spi_device_flash_all	1.949m	197.167ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.940s	1.499ms	1	1	100.00
		spi_device_flash_all	1.949m	197.167ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	17.360s	34.019ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	7.570s	353.196us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	7.570s	353.196us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	7.570s	353.196us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	10.270s	1.627ms	1	1	100.00
		spi_device_read_buffer_direct	3.870s	737.113us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	7.570s	353.196us	1	1	100.00
		spi_device_flash_all	1.949m	197.167ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.949m	197.167ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.949m	197.167ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	7.780s	885.467us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	7.780s	885.467us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.228m	24.792ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.880s	1.978ms	1	1	100.00
V2	stress_all	spi_device_stress_all	49.320s	3.680ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.480s	78.910us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.510s	85.408us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.650s	1.600ms	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.650s	1.600ms	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.800s	66.860us	1	1	100.00
		spi_device_csr_rw	2.800s	39.047us	1	1	100.00
		spi_device_csr_aliasing	16.770s	946.242us	1	1	100.00
		spi_device_same_csr_outstanding	3.780s	768.191us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.800s	66.860us	1	1	100.00
		spi_device_csr_rw	2.800s	39.047us	1	1	100.00
		spi_device_csr_aliasing	16.770s	946.242us	1	1	100.00
		spi_device_same_csr_outstanding	3.780s	768.191us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.240s	101.461us	1	1	100.00
		spi_device_tl_intg_err	13.720s	596.418us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	13.720s	596.418us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.683m	94.927ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.3435984983056491523743090772972307825155229398739908590021473161236136542537
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4349736 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[35])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4349736 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4349736 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[931])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.33865028836136122521708835659590675016153947317474528056432047843296229574444
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3714858 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbd98bf [101111011001100010111111] vs 0x0 [0])
        UVM_ERROR @   3775858 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x103c82 [100000011110010000010] vs 0x0 [0])
        UVM_ERROR @   3809858 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe40611 [111001000000011000010001] vs 0x0 [0])
        UVM_ERROR @   3842858 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfafaef [111110101111101011101111] vs 0x0 [0])
        UVM_ERROR @   3887858 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5ff50e [10111111111010100001110] vs 0x0 [0])