SPI_DEVICE/2P Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	6.668m	662.064ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.700s	172.017us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.810s	126.247us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.330s	16.369ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.180s	807.252us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.910s	51.697us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.810s	126.247us	1	1	100.00
		spi_device_csr_aliasing	11.180s	807.252us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.640s	11.600us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.220s	73.515us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.620s	41.460us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.780s	25.899us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.570s	22.562us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	3.380s	598.231us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.380s	598.231us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	17.720s	39.402ms	1	1	100.00
		spi_device_tpm_sts_read	1.600s	87.187us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	2.480s	206.617us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.270s	649.296us	1	1	100.00
		spi_device_flash_all	29.150s	7.400ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.120s	1.959ms	1	1	100.00
		spi_device_flash_all	29.150s	7.400ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.120s	1.959ms	1	1	100.00
		spi_device_flash_all	29.150s	7.400ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	29.150s	7.400ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	14.090s	21.319ms	1	1	100.00
		spi_device_flash_all	29.150s	7.400ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	14.090s	21.319ms	1	1	100.00
		spi_device_flash_all	29.150s	7.400ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	14.090s	21.319ms	1	1	100.00
		spi_device_flash_all	29.150s	7.400ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	14.090s	21.319ms	1	1	100.00
		spi_device_flash_all	29.150s	7.400ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	14.090s	21.319ms	1	1	100.00
		spi_device_flash_all	29.150s	7.400ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	9.300s	4.927ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	12.540s	615.664us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	12.540s	615.664us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	12.540s	615.664us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.210s	7.957ms	1	1	100.00
		spi_device_read_buffer_direct	10.380s	1.527ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	12.540s	615.664us	1	1	100.00
		spi_device_flash_all	29.150s	7.400ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	29.150s	7.400ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	29.150s	7.400ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.880s	640.835us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.880s	640.835us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	6.668m	662.064ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.582m	131.483ms	1	1	100.00
V2	stress_all	spi_device_stress_all	4.415m	43.366ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.540s	29.114us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.640s	155.538us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.100s	237.769us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.100s	237.769us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.700s	172.017us	1	1	100.00
		spi_device_csr_rw	1.810s	126.247us	1	1	100.00
		spi_device_csr_aliasing	11.180s	807.252us	1	1	100.00
		spi_device_same_csr_outstanding	2.670s	183.350us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.700s	172.017us	1	1	100.00
		spi_device_csr_rw	1.810s	126.247us	1	1	100.00
		spi_device_csr_aliasing	11.180s	807.252us	1	1	100.00
		spi_device_same_csr_outstanding	2.670s	183.350us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.240s	405.942us	1	1	100.00
		spi_device_tl_intg_err	10.770s	682.190us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.770s	682.190us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	25.010s	2.714ms	1	1	100.00
		TOTAL			33	33	100.00