SPI_HOST Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	8.000s	783.854us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	79.399us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	46.817us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	1.383ms	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	65.232us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	62.111us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	46.817us	1	1	100.00
		spi_host_csr_aliasing	4.000s	65.232us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	39.349us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	20.338us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	36.475us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	74.850us	1	1	100.00
		spi_host_error_cmd	3.000s	52.617us	1	1	100.00
		spi_host_event	15.000s	6.213ms	1	1	100.00
V2	clock_rate	spi_host_speed	5.000s	199.710us	1	1	100.00
V2	speed	spi_host_speed	5.000s	199.710us	1	1	100.00
V2	chip_select_timing	spi_host_speed	5.000s	199.710us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	6.000s	203.031us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	68.791us	1	1	100.00
V2	cpol_cpha	spi_host_speed	5.000s	199.710us	1	1	100.00
V2	full_cycle	spi_host_speed	5.000s	199.710us	1	1	100.00
V2	duplex	spi_host_smoke	8.000s	783.854us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	8.000s	783.854us	1	1	100.00
V2	stress_all	spi_host_stress_all	28.000s	4.333ms	1	1	100.00
V2	spien	spi_host_spien	1.083m	10.899ms	1	1	100.00
V2	stall	spi_host_status_stall	13.000s	708.239us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	202.371us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	74.850us	1	1	100.00
V2	alert_test	spi_host_alert_test	3.000s	49.243us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	17.490us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	150.438us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	150.438us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	79.399us	1	1	100.00
		spi_host_csr_rw	4.000s	46.817us	1	1	100.00
		spi_host_csr_aliasing	4.000s	65.232us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	147.032us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	79.399us	1	1	100.00
		spi_host_csr_rw	4.000s	46.817us	1	1	100.00
		spi_host_csr_aliasing	4.000s	65.232us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	147.032us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	587.078us	1	1	100.00
		spi_host_sec_cm	4.000s	46.213us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	587.078us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.317m	5.136ms	1	1	100.00
		TOTAL			26	26	100.00