SRAM_CTRL/RET Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	7.980s	697.194us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.610s	35.082us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.540s	16.745us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.420s	413.558us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.910s	61.331us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.140s	98.566us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.540s	16.745us	1	1	100.00
		sram_ctrl_csr_aliasing	1.910s	61.331us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.630s	195.939us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.780s	195.014us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.296m	2.719ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.902m	27.816ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	41.220s	13.479ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.968m	8.234ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.010s	183.150us	1	1	100.00
V2	executable	sram_ctrl_executable	2.042m	1.710ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	17.060s	1.045ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.038m	5.734ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	3.090s	176.849us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	33.990s	125.891us	1	1	100.00
		sram_ctrl_throughput_w_readback	13.490s	134.689us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.179m	5.347ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.770s	34.860us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	10.590m	62.893ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	2.100s	14.174us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.000s	269.409us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.000s	269.409us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.610s	35.082us	1	1	100.00
		sram_ctrl_csr_rw	1.540s	16.745us	1	1	100.00
		sram_ctrl_csr_aliasing	1.910s	61.331us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.780s	40.686us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.610s	35.082us	1	1	100.00
		sram_ctrl_csr_rw	1.540s	16.745us	1	1	100.00
		sram_ctrl_csr_aliasing	1.910s	61.331us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.780s	40.686us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.660s	391.984us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.530s	3.249us	0	1	0.00
		sram_ctrl_tl_intg_err	3.430s	197.220us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.530s	3.249us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.430s	197.220us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.179m	5.347ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.179m	5.347ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.540s	16.745us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	2.042m	1.710ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	2.042m	1.710ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	2.042m	1.710ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.010s	183.150us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.350s	156.793us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.660s	391.984us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.950s	45.140us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	7.980s	697.194us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	7.980s	697.194us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	2.042m	1.710ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.530s	3.249us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.010s	183.150us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.530s	3.249us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.530s	3.249us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	7.980s	697.194us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.530s	3.249us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.898m	3.835ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			28	31	90.32

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.81959306825635054299679248176997886387586108218129030407532976468117658659480
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 156793444 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 156793444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.sram_ctrl_stress_all_with_rand_reset.2872083630464116922177779455202266632570894460039465124866591557995462851064
      Line 418, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3835267407 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3835267407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.96344259489330657904160267768016838176425092550180493121057601006169904519711
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3248626 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3248626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---