SYSRST_CTRL Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 2.640s 2.137ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 2.370s 2.491ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 2.150s 2.296ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.350s 2.533ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 3.650s 4.036ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 2.460s 2.059ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 2.442m 76.623ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 9.880s 2.986ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.430s 2.080ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 2.460s 2.059ms 1 1 100.00
sysrst_ctrl_csr_aliasing 9.880s 2.986ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.378m 82.415ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 1.210m 78.393ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 3.430s 3.609ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 5.060s 3.501ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 2.840s 2.529ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 3.310s 2.248ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 6.920s 3.232ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 6.650s 2.615ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 3.690s 7.043ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 56.980s 30.719ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 26.060s 12.284ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 3.310s 2.023ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 8.860s 2.014ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 6.080s 2.051ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 6.080s 2.051ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 3.650s 4.036ms 1 1 100.00
sysrst_ctrl_csr_rw 2.460s 2.059ms 1 1 100.00
sysrst_ctrl_csr_aliasing 9.880s 2.986ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.160s 7.598ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 3.650s 4.036ms 1 1 100.00
sysrst_ctrl_csr_rw 2.460s 2.059ms 1 1 100.00
sysrst_ctrl_csr_aliasing 9.880s 2.986ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.160s 7.598ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 1.282m 42.200ms 1 1 100.00
sysrst_ctrl_tl_intg_err 43.730s 42.549ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 43.730s 42.549ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 10.360s 8.320ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00