UART Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	10.370s	5.690ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.510s	14.093us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.670s	34.520us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.070s	263.150us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.760s	66.072us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.730s	32.412us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.670s	34.520us	1	1	100.00
		uart_csr_aliasing	1.760s	66.072us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.666m	189.689ms	1	1	100.00
V2	parity	uart_smoke	10.370s	5.690ms	1	1	100.00
		uart_tx_rx	1.666m	189.689ms	1	1	100.00
V2	parity_error	uart_intr	8.069m	444.779ms	1	1	100.00
		uart_rx_parity_err	2.423m	102.375ms	1	1	100.00
V2	watermark	uart_tx_rx	1.666m	189.689ms	1	1	100.00
		uart_intr	8.069m	444.779ms	1	1	100.00
V2	fifo_full	uart_fifo_full	23.560s	21.750ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	27.960s	95.704ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	41.220s	115.863ms	0	1	0.00
V2	rx_frame_err	uart_intr	8.069m	444.779ms	1	1	100.00
V2	rx_break_err	uart_intr	8.069m	444.779ms	1	1	100.00
V2	rx_timeout	uart_intr	8.069m	444.779ms	1	1	100.00
V2	perf	uart_perf	3.967m	10.194ms	1	1	100.00
V2	sys_loopback	uart_loopback	10.090s	14.518ms	1	1	100.00
V2	line_loopback	uart_loopback	10.090s	14.518ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	21.480s	16.706ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	37.750s	31.551ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	5.330s	9.521ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	6.320s	3.719ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.524m	222.164ms	1	1	100.00
V2	stress_all	uart_stress_all	7.514m	118.748ms	1	1	100.00
V2	alert_test	uart_alert_test	1.620s	19.791us	1	1	100.00
V2	intr_test	uart_intr_test	1.500s	108.374us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.990s	44.129us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.990s	44.129us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.510s	14.093us	1	1	100.00
		uart_csr_rw	1.670s	34.520us	1	1	100.00
		uart_csr_aliasing	1.760s	66.072us	1	1	100.00
		uart_same_csr_outstanding	1.610s	143.298us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.510s	14.093us	1	1	100.00
		uart_csr_rw	1.670s	34.520us	1	1	100.00
		uart_csr_aliasing	1.760s	66.072us	1	1	100.00
		uart_same_csr_outstanding	1.610s	143.298us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	1.680s	232.317us	1	1	100.00
		uart_tl_intg_err	2.100s	200.766us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.100s	200.766us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	20.570s	1.956ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 1 failures:

  • Test uart_fifo_reset has 1 failures.

    • 0.uart_fifo_reset.102155109822984913693429653317950122892382893417088184396110650509304906004201
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_fifo_reset/latest/run.log

        UVM_ERROR @   4881877 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 3290324827 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/9
        UVM_INFO @ 3292324843 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/9
        UVM_INFO @ 4967296576 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/9
        UVM_INFO @ 5642468644 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/9
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.20730350022537363174963507183490102664216292340680866996560510157481148528675
      Line 72, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 16217696587 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0
        UVM_ERROR @ 16217706587 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 16217716587 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 238 [0xee]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 16217726587 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 16217736587 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 119 [0x77]) reg name: uart_reg_block.rdata