CHIP Simulation Results

Wednesday June 11 2025 18:32:34 UTC

GitHub Revision: `209351c`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.392m	2.780ms	1	1	100.00
		chip_sw_example_rom	18.799s		0	1	0.00
		chip_sw_example_manufacturer	2.562m	3.139ms	1	1	100.00
		chip_sw_example_concurrency	1.744m	2.855ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.153m	5.358ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.261m	3.856ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	3.940m	5.471ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.236h	37.995ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	41.470s	2.665ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.236h	37.995ms	1	1	100.00
		chip_csr_rw	2.261m	3.856ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	8.360s	249.570us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.673m	3.778ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.673m	3.778ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.673m	3.778ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.697m	3.401ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.697m	3.401ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.559m	3.830ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.766m	4.133ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.026m	4.495ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.367m	8.872ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	16.754m	8.928ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.586m	4.155ms	1	1	100.00
V1		TOTAL			16	18	88.89
V2	chip_pin_mux	chip_padctrl_attributes	2.439m	4.013ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.439m	4.013ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.491m	3.289ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.005m	6.275ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.158m	3.342ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	13.471m	13.768ms	1	1	100.00
		chip_tap_straps_testunlock0	6.932m	7.544ms	1	1	100.00
		chip_tap_straps_rma	5.459m	5.817ms	1	1	100.00
		chip_tap_straps_prod	13.969m	13.588ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.733m	3.154ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	10.509m	8.738ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.432m	5.836ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.432m	5.836ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.577m	6.788ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	21.966m	16.641ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.139m	3.736ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.560m	6.242ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.076m	17.827ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.454m	2.371ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	7.882m	5.429ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.851m	3.319ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	21.413m	10.402ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.759m	3.028ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.281m	5.037ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.116m	2.294ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.746m	2.942ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.520m	7.987ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.443m	4.430ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.234m	3.084ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.443m	4.430ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.488m	2.545ms	1	1	100.00
		chip_sw_aes_smoketest	2.650m	3.451ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.248m	3.324ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.672m	3.228ms	1	1	100.00
		chip_sw_csrng_smoketest	2.608m	2.702ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.062m	3.538ms	1	1	100.00
		chip_sw_gpio_smoketest	2.968m	2.924ms	1	1	100.00
		chip_sw_hmac_smoketest	2.452m	2.915ms	1	1	100.00
		chip_sw_kmac_smoketest	2.744m	2.954ms	1	1	100.00
		chip_sw_otbn_smoketest	18.580m	11.261ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.349m	4.883ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.525m	6.286ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.264m	2.890ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.383m	2.896ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.909m	2.365ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.631m	2.326ms	1	1	100.00
		chip_sw_uart_smoketest	2.576m	3.391ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.781m	3.317ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	6.587m	4.474ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.036h	61.144ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.671m	15.194ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.841m	7.061ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.383m	3.010ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.367m	3.386ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.773h	54.586ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.846h	57.211ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	49.120s	2.368ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	49.120s	2.368ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.236h	37.995ms	1	1	100.00
		chip_same_csr_outstanding	45.281m	30.439ms	1	1	100.00
		chip_csr_hw_reset	2.153m	5.358ms	1	1	100.00
		chip_csr_rw	2.261m	3.856ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.236h	37.995ms	1	1	100.00
		chip_same_csr_outstanding	45.281m	30.439ms	1	1	100.00
		chip_csr_hw_reset	2.153m	5.358ms	1	1	100.00
		chip_csr_rw	2.261m	3.856ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	23.970s	1.132ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.820s	37.828us	1	1	100.00
		xbar_smoke_large_delays	57.540s	9.817ms	1	1	100.00
		xbar_smoke_slow_rsp	48.610s	5.175ms	1	1	100.00
		xbar_random_zero_delays	28.060s	481.441us	1	1	100.00
		xbar_random_large_delays	3.473m	37.206ms	1	1	100.00
		xbar_random_slow_rsp	1.448m	10.369ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	4.940s	16.255us	1	1	100.00
		xbar_error_and_unmapped_addr	29.340s	1.254ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	8.250s	238.599us	1	1	100.00
		xbar_error_and_unmapped_addr	29.340s	1.254ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	16.750s	218.725us	1	1	100.00
		xbar_access_same_device_slow_rsp	1.821m	12.973ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	26.580s	1.353ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	16.730s	653.386us	1	1	100.00
		xbar_stress_all_with_error	2.135m	6.880ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.509m	2.718ms	1	1	100.00
		xbar_stress_all_with_reset_error	4.229m	10.222ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.671m	15.194ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	36.917m	28.261ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	41.073m	15.321ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.005m	10.479ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	39.541m	16.097ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.027m	16.080ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	41.003m	15.469ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	41.052m	14.842ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	20.370s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	19.460s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.750s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.750s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	17.060s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.200s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	16.500s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.960s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.790s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.910s	10.260us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	15.860s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.550s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	15.430s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.040s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	15.660s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.030s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	15.660s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	15.510s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	15.690s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.150s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.140s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.690s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.730s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.190s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	15.850s	10.400us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	30.387m	11.748ms	1	1	100.00
		rom_e2e_asm_init_dev	38.170m	15.860ms	1	1	100.00
		rom_e2e_asm_init_prod	37.504m	15.649ms	1	1	100.00
		rom_e2e_asm_init_prod_end	38.247m	16.113ms	1	1	100.00
		rom_e2e_asm_init_rma	37.306m	15.328ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	38.145m	14.636ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	38.302m	15.622ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	38.404m	14.969ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	38.789m	15.746ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.934m	35.397ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.934m	35.397ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.473m	2.993ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.454m	2.371ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.797m	2.804ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.807m	2.358ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	22.040m	10.677ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.406m	2.943ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.401m	4.880ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.401m	6.044ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.657m	4.875ms	1	1	100.00
		chip_plic_all_irqs_10	4.463m	3.970ms	1	1	100.00
		chip_plic_all_irqs_20	5.362m	4.467ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.605m	3.234ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.992m	13.824ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.728m	5.889ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.348m	2.683ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	13.357m	12.616ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.430m	8.735ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.492m	5.420ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.972m	8.101ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.919h	254.518ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.015m	3.349ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.349m	4.883ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.015m	3.349ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.549m	7.344ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.549m	7.344ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.930m	6.774ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.465m	5.451ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.348m	6.026ms	1	1	100.00
		chip_sw_aes_idle	1.807m	2.358ms	1	1	100.00
		chip_sw_hmac_enc_idle	1.924m	2.828ms	1	1	100.00
		chip_sw_kmac_idle	2.192m	2.823ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	2.509m	3.816ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.065m	3.729ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.574m	4.935ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.011m	4.065ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.505m	11.405ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.799m	3.802ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.507m	4.760ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.125m	3.735ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.475m	4.140ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.350m	4.369ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.192m	4.820ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.577m	6.788ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	5.188m	7.894ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.125m	3.735ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.475m	4.140ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.139m	3.736ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.560m	6.242ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.076m	17.827ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.454m	2.371ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	7.882m	5.429ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.851m	3.319ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	21.413m	10.402ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.759m	3.028ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.281m	5.037ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.116m	2.294ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.224m	2.563ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.063m	4.951ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.657m	6.704ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	51.592m	24.482ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.291m	3.503ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.837m	2.929ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.590m	8.257ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.994m	3.027ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.687m	3.939ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	19.784m	24.395ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	4.074h	195.823ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.577m	6.788ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	4.958m	3.801ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.543m	3.605ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.401m	6.044ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	16.430m	8.735ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.069m	6.646ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	1.671m	2.548ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.895m	6.924ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.019m	2.149ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	56.112m	20.536ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.386m	3.522ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.946m	6.365ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.386m	3.522ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.069m	6.646ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.263m	2.490ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	16.416m	16.650ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	7.819m	4.896ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.560m	6.242ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	4.439m	3.943ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.139m	3.736ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	55.043m	42.911ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	16.416m	16.650ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.326m	3.397ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	16.003m	9.037ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.065m	5.155ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	55.043m	42.911ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.065m	5.155ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.065m	5.155ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.065m	5.155ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.065m	5.155ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.401m	6.044ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.231m	3.383ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.924m	5.035ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	4.657m	4.561ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	4.657m	4.561ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.112m	2.607ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.851m	3.319ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	1.924m	2.828ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.872m	3.184ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.493m	4.154ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.813m	5.746ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	3.962m	4.379ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.385m	4.608ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.454m	3.548ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	16.003m	9.037ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	21.413m	10.402ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	18.746m	8.917ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	22.040m	10.677ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	37.286m	13.595ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.893m	2.872ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.381m	3.248ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.759m	3.028ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	16.003m	9.037ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	4.526m	5.157ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.374m	2.656ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	14.202m	7.182ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.192m	2.823ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.401m	4.880ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	13.471m	13.768ms	1	1	100.00
		chip_tap_straps_rma	5.459m	5.817ms	1	1	100.00
		chip_tap_straps_prod	13.969m	13.588ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.957m	3.110ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	4.526m	5.157ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	4.526m	5.157ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	4.526m	5.157ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	10.569m	5.850ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.065m	5.155ms	1	1	100.00
		chip_sw_flash_rma_unlocked	55.043m	42.911ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.676m	2.491ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.660m	6.887ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.896m	7.121ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.017m	6.815ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.526m	5.157ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.003m	9.037ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.875m	8.367ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.638m	7.173ms	1	1	100.00
		chip_prim_tl_access	1.231m	3.383ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	5.188m	7.894ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.799m	3.802ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.507m	4.760ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.125m	3.735ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.475m	4.140ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.350m	4.369ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.192m	4.820ms	1	1	100.00
		chip_tap_straps_dev	13.471m	13.768ms	1	1	100.00
		chip_tap_straps_rma	5.459m	5.817ms	1	1	100.00
		chip_tap_straps_prod	13.969m	13.588ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.531m	10.967ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.117m	3.508ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.401m	3.478ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.613m	3.166ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.793m	3.263ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	19.125m	31.107ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.531m	10.967ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.029h	46.536ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.138h	47.733ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.384m	8.174ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	58.946m	46.439ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	19.125m	31.107ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	50.850s	2.643ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	59.220s	2.410ms	1	1	100.00
		rom_volatile_raw_unlock	56.250s	2.515ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.944m	16.925ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.076m	17.827ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.348m	6.026ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.348m	6.026ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.348m	6.026ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.372m	3.735ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	4.526m	5.157ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	16.416m	16.650ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.372m	3.735ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.003m	9.037ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.054m	4.717ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.909m	3.005ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	16.416m	16.650ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.372m	3.735ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.003m	9.037ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.054m	4.717ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.909m	3.005ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	4.526m	5.157ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.108m	4.066ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.957m	3.110ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.676m	2.491ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.660m	6.887ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.896m	7.121ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.017m	6.815ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.526m	5.157ms	1	1	100.00
		chip_prim_tl_access	1.231m	3.383ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.231m	3.383ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.846m	7.793ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.691m	6.909ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	13.493m	25.551ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.517m	8.057ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.083m	8.194ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.198m	6.100ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	16.646m	27.355ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	15.787m	13.996ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.549m	7.344ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.029m	11.225ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.610m	3.823ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.691m	6.909ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.983m	4.212ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	39.178m	43.918ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.951m	6.770ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.505m	6.494ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.839m	21.640ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.347m	7.864ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	13.082m	9.194ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	21.962m	27.922ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.044m	2.237ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.401m	6.044ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.875m	8.367ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.875m	8.367ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	13.082m	9.194ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.839m	21.640ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.610m	3.823ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.349m	4.883ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.239m	4.259ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.138m	4.818ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.038m	3.033ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.992m	13.824ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.165m	3.568ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.401m	6.044ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	10.492m	5.420ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.877m	4.616ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.388m	4.600ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.814m	2.549ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.909m	3.005ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.138m	4.818ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.138m	4.818ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	13.248m	12.918ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	12.328m	13.040ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.239m	4.259ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.414m	5.211ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.730m	5.943ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	5.459m	5.817ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.531m	10.967ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.657m	4.875ms	1	1	100.00
		chip_plic_all_irqs_10	4.463m	3.970ms	1	1	100.00
		chip_plic_all_irqs_20	5.362m	4.467ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.122m	3.563ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	1.824m	2.476ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.671m	15.194ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.115m	7.150ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.505m	3.475ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.911m	3.169ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.428m	2.647ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.054m	4.717ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.281m	5.037ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	8.205m	8.523ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.195m	8.816ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.638m	7.173ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.401m	6.044ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.432m	5.836ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.347m	7.864ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	17.556m	24.157ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.213m	3.107ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.052m	4.109ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.155m	4.241ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	17.556m	24.157ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	17.556m	24.157ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	33.571m	21.216ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	33.571m	21.216ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	2.831m	5.306ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.934m	35.397ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.023m	3.029ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.702m	3.197ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.326m	3.565ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.579m	3.626ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.602m	8.101ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.321h	31.286ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	28.271m	11.371ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.266m	2.526ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.925m	2.989ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.212m	2.765ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.441h	72.593ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.710m	5.967ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	18.619m	10.971ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.961m	12.480ms	1	1	100.00
		rom_e2e_jtag_debug_rma	18.097m	11.596ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.504m	4.186ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.083m	4.088ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.102m	3.879ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.300s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.360m	5.504ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.027m	2.863ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	8.929m	3.723ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	12.182m	7.007ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.359m	2.854ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.069m	5.221ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.060m	2.260ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.343m	5.739ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.308m	6.721ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.442m	5.124ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	13.082m	9.194ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	18.619m	10.971ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.961m	12.480ms	1	1	100.00
		rom_e2e_jtag_debug_rma	18.097m	11.596ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.954m	5.133ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.401m	6.044ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.443h	37.881ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.443h	37.881ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.427m	3.251ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.697m	3.401ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	49.658m	18.464ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.938m	2.377ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	13.721s		0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.289m	2.500ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.444m	2.295ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.276m	4.407ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.676s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.894m	3.288ms	1	1	100.00
		TOTAL			283	325	87.08

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.22161808053796592055044246143493750423383297599203689406759479791395217143209
    Line 621, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4931407106520328083372361546140996898728498435537711011448018779194250956765
    Line 651, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.62829351372649621732532420156596039764484205721173682296642583062999442718305
    Line 682, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.101447058527025857503997038719102833799071588721405199824067043986727701847797
    Line 622, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.18970377691667083398195856513043478319949758665349854732021980910388478105972
    Line 658, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.25206555635517183262484795152791695811189672249397866547105344593228508127446
    Line 621, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.47464296981509609789267096218765611005757606891943135909797259368362939229647
    Line 661, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.74981832464625568727051151363837703595916741884634376416637664721989200538776
    Line 589, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.11147330796496375885870563966625571031579676121381791816780747757752734912797
    Line 608, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.26897345912695245852912365524503138777488474800324962804280430324106599978191
    Line 636, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 4 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.63890032814154620339983546533943532842535464294135773905905080290831429035408
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests:example_test_from_rom_sim_dv".
  Building "//sw/device/tests:example_test_from_rom_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true --//util/design/data:img_seed=63890032814154620339983546533943532842535464294135773905905080290831429035408 //sw/device/tests:example_test_from_rom_sim_dv
  2025/06/11 18:50:23 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
  Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
  FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 36

Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.

0.chip_sw_rstmgr_rst_cnsty_escalation.12308871514880991917335935240239232170819299465339823601791951283376608609493
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv".
  Building "//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true --//util/design/data:img_seed=12308871514880991917335935240239232170819299465339823601791951283376608609493 //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv
  2025/06/11 18:50:27 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
  Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
  FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 36

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.69625746289870764631866258535413855721062059794381711119656609335358219408444
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.149s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.24002671716319719478371039162666091283887179382894369749414408870673062267637
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.160s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.31911265734521211995143420282537526649850196940423566166422188274861703986472
    Line 791, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.66078310454901806625747619336389794126607388993934163663042354320726119070942
    Line 701, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.98552645293950629790629418063794619432474259260175128465826171672132577393531
    Line 647, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.87602568098086493134561612206492581376753497828194265718635317517507376523738
    Line 808, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.27233077020303163526710787555966222568573842107601504640057057232791754176202
    Line 626, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.103906826675669935103170433039063524955405910235649454747050175530138021679722
    Line 763, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4265704292401418862738179903973462929496156357774302868137192874800695188034
    Line 718, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.39756693090614991161893177884738744955520839867035365680064661029057100532205
    Line 760, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3288.765000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3288.765000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.57106675329668561999348745410774489470857501162294419971021905207277016421052
    Line 484, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3474.813840 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3474.813840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@97123) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.75842367522229265891389316913124749549893037033939120114770740777739573174220
Line 453, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4817.742396 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@97123) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4817.742396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.82749032184035363919338668292240806882123447062686165311149570205208246607429
    Line 443, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 35396.782755 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 35396.782755 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.103935730479762431385806771840308730940677649830261982622201863372777055630555
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2942.853550 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 2942.853550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.31538917111597427415508893734543363462045103911723059626193295423539102384784
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2682.637150 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2682.637150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.23982399830555160887210088407006788504787362335075602149748392241055793849395
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2547.571685 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2547.571685 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32159) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.76244566117188814485502972731456950304104186159251203129781299578662651026527
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2367.692616 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32159) { a_addr: 'h10554  a_data: 'ha7ca95f2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h4  a_user: 'h19245  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2367.692616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.44253765467109980868538445821208644203700864407277531901182259110867981008983
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2764.954354 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2764.954354 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.87038706741340283738195055896490906527148193745371150836051636595191203598158
    Line 420, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3009.750000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3009.750000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.13103019987385699238587596670261275057980772853460407843673448040414100885845
    Line 430, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3386.313000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3386.313000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.104791944215875511976408178884133928925308249473432334026785925695066186933805
    Line 443, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 16641.299404 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 16641.299404 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2300891616131627673110561136089715361452424841990937344589219135509383965143
    Line 741, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.111447753608401685787872708487033838758568207625373061944295489645997904387009
    Line 718, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32997) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.21261115632342337080395969591571672878940188721592672532950773990930410080596
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2665.295724 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32997) { a_addr: 'h10708  a_data: 'h22e942e8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h4  a_user: 'h18d71  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2665.295724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---