ADC_CTRL Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	11.270s	6.010ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.100s	1.197ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.700s	472.469us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	16.610s	27.054ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.720s	457.284us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.140s	359.596us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.700s	472.469us	1	1	100.00
		adc_ctrl_csr_aliasing	2.720s	457.284us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	3.990m	160.766ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	9.174m	327.004ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	14.107m	490.347ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.372m	327.486ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	15.714m	549.361ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.292m	411.033ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	16.901m	600.000ms	0	1	0.00
V2	clock_gating	adc_ctrl_clock_gating	2.249m	161.974ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.630s	4.071ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	21.810s	25.340ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.817m	127.548ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	4.636m	749.008ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.110s	300.055us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.330s	287.524us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.480s	413.369us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.480s	413.369us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.100s	1.197ms	1	1	100.00
		adc_ctrl_csr_rw	1.700s	472.469us	1	1	100.00
		adc_ctrl_csr_aliasing	2.720s	457.284us	1	1	100.00
		adc_ctrl_same_csr_outstanding	10.790s	4.985ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.100s	1.197ms	1	1	100.00
		adc_ctrl_csr_rw	1.700s	472.469us	1	1	100.00
		adc_ctrl_csr_aliasing	2.720s	457.284us	1	1	100.00
		adc_ctrl_same_csr_outstanding	10.790s	4.985ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	15.870s	7.947ms	1	1	100.00
		adc_ctrl_tl_intg_err	2.820s	5.215ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	2.820s	5.215ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	13.080s	3.049ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 0.adc_ctrl_filters_both.81091980050738710220535279841156014958525200994365640639923228428033569876872
      Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---