EDN Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.170s 17.600us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.700s 24.113us 1 1 100.00
V1 csr_rw edn_csr_rw 1.680s 19.708us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.840s 524.288us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 2.390s 95.571us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.910s 15.899us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.680s 19.708us 1 1 100.00
edn_csr_aliasing 2.390s 95.571us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.640s 48.266us 1 1 100.00
V2 csrng_commands edn_genbits 2.640s 48.266us 1 1 100.00
V2 genbits edn_genbits 2.640s 48.266us 1 1 100.00
V2 interrupts edn_intr 2.140s 21.358us 1 1 100.00
V2 alerts edn_alert 1.790s 78.554us 1 1 100.00
V2 errs edn_err 1.800s 27.849us 1 1 100.00
V2 disable edn_disable 1.580s 33.759us 1 1 100.00
edn_disable_auto_req_mode 2.350s 48.045us 1 1 100.00
V2 stress_all edn_stress_all 4.870s 759.892us 1 1 100.00
V2 intr_test edn_intr_test 2.200s 137.093us 1 1 100.00
V2 alert_test edn_alert_test 1.900s 48.547us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.340s 31.813us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.340s 31.813us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.700s 24.113us 1 1 100.00
edn_csr_rw 1.680s 19.708us 1 1 100.00
edn_csr_aliasing 2.390s 95.571us 1 1 100.00
edn_same_csr_outstanding 2.320s 28.402us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.700s 24.113us 1 1 100.00
edn_csr_rw 1.680s 19.708us 1 1 100.00
edn_csr_aliasing 2.390s 95.571us 1 1 100.00
edn_same_csr_outstanding 2.320s 28.402us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 7.320s 3.241ms 1 1 100.00
edn_tl_intg_err 4.160s 212.258us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.820s 17.589us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.790s 78.554us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.320s 3.241ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.320s 3.241ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.320s 3.241ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.320s 3.241ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.790s 78.554us 1 1 100.00
edn_sec_cm 7.320s 3.241ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.790s 78.554us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.160s 212.258us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets