4ec736f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | entropy_src_smoke | 4.000s | 45.359us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | entropy_src_csr_hw_reset | 5.000s | 93.692us | 1 | 1 | 100.00 |
| V1 | csr_rw | entropy_src_csr_rw | 4.000s | 14.594us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | entropy_src_csr_bit_bash | 14.000s | 806.690us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | entropy_src_csr_aliasing | 7.000s | 211.461us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | entropy_src_csr_mem_rw_with_rand_reset | 4.000s | 138.043us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | entropy_src_csr_rw | 4.000s | 14.594us | 1 | 1 | 100.00 |
| entropy_src_csr_aliasing | 7.000s | 211.461us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | firmware | entropy_src_smoke | 4.000s | 45.359us | 1 | 1 | 100.00 |
| entropy_src_rng | 12.000s | 1.667ms | 0 | 1 | 0.00 | ||
| entropy_src_fw_ov | 1.083m | 15.060ms | 1 | 1 | 100.00 | ||
| V2 | firmware_mode | entropy_src_fw_ov | 1.083m | 15.060ms | 1 | 1 | 100.00 |
| V2 | rng_mode | entropy_src_rng | 12.000s | 1.667ms | 0 | 1 | 0.00 |
| V2 | rng_max_rate | entropy_src_rng_max_rate | 4.000s | 10.198us | 0 | 1 | 0.00 |
| V2 | health_checks | entropy_src_rng | 12.000s | 1.667ms | 0 | 1 | 0.00 |
| V2 | conditioning | entropy_src_rng | 12.000s | 1.667ms | 0 | 1 | 0.00 |
| V2 | interrupts | entropy_src_rng | 12.000s | 1.667ms | 0 | 1 | 0.00 |
| entropy_src_intr | 6.000s | 135.749us | 1 | 1 | 100.00 | ||
| V2 | alerts | entropy_src_rng | 12.000s | 1.667ms | 0 | 1 | 0.00 |
| entropy_src_functional_alerts | 5.000s | 64.814us | 1 | 1 | 100.00 | ||
| V2 | stress_all | entropy_src_stress_all | 7.000s | 1.195ms | 0 | 1 | 0.00 |
| V2 | functional_errors | entropy_src_functional_errors | 5.000s | 181.721us | 1 | 1 | 100.00 |
| V2 | firmware_ov_read_contiguous_data | entropy_src_fw_ov_contiguous | 5.000s | 95.867us | 1 | 1 | 100.00 |
| V2 | intr_test | entropy_src_intr_test | 4.000s | 17.939us | 1 | 1 | 100.00 |
| V2 | alert_test | entropy_src_alert_test | 4.000s | 25.551us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | entropy_src_tl_errors | 5.000s | 53.437us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | entropy_src_tl_errors | 5.000s | 53.437us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | entropy_src_csr_hw_reset | 5.000s | 93.692us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 4.000s | 14.594us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 7.000s | 211.461us | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 7.000s | 163.923us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | entropy_src_csr_hw_reset | 5.000s | 93.692us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 4.000s | 14.594us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 7.000s | 211.461us | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 7.000s | 163.923us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 9 | 12 | 75.00 | |||
| V2S | tl_intg_err | entropy_src_sec_cm | 5.000s | 220.141us | 1 | 1 | 100.00 |
| entropy_src_tl_intg_err | 5.000s | 1.475ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_regwen | entropy_src_rng | 12.000s | 1.667ms | 0 | 1 | 0.00 |
| entropy_src_cfg_regwen | 5.000s | 190.269us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_mubi | entropy_src_rng | 12.000s | 1.667ms | 0 | 1 | 0.00 |
| V2S | sec_cm_config_redun | entropy_src_rng | 12.000s | 1.667ms | 0 | 1 | 0.00 |
| V2S | sec_cm_intersig_mubi | entropy_src_rng | 12.000s | 1.667ms | 0 | 1 | 0.00 |
| entropy_src_fw_ov | 1.083m | 15.060ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_main_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 181.721us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 220.141us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ack_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 181.721us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 220.141us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_rng_bkgn_chk | entropy_src_rng | 12.000s | 1.667ms | 0 | 1 | 0.00 |
| V2S | sec_cm_fifo_ctr_redun | entropy_src_functional_errors | 5.000s | 181.721us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 220.141us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_redun | entropy_src_functional_errors | 5.000s | 181.721us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 220.141us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_local_esc | entropy_src_functional_errors | 5.000s | 181.721us | 1 | 1 | 100.00 |
| V2S | sec_cm_esfinal_rdata_bus_consistency | entropy_src_functional_alerts | 5.000s | 64.814us | 1 | 1 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | entropy_src_tl_intg_err | 5.000s | 1.475ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | external_health_tests | entropy_src_rng_with_xht_rsps | 7.000s | 440.221us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 18 | 22 | 81.82 |
UVM_ERROR (entropy_src_scoreboard.sv:2073) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.recov_alert_sts has 2 failures:
Test entropy_src_rng has 1 failures.
0.entropy_src_rng.96131749281231928981039836784324340178880638895123957541621779455375051149770
Line 469, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng/latest/run.log
UVM_ERROR @ 1667215114 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2 [0x2]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 1667215114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test entropy_src_rng_with_xht_rsps has 1 failures.
0.entropy_src_rng_with_xht_rsps.46193021091581415706832091835038469286195748645493924163636847230104586674720
Line 310, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_with_xht_rsps/latest/run.log
UVM_ERROR @ 440220638 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 131072 [0x20000]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 440220638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/fusesoc-work/src/lowrisc_fpv_entropy_src_csr_assert_*/entropy_src_csr_assert_fpv.sv,306): Assertion conf_rd_A has failed has 1 failures:
0.entropy_src_rng_max_rate.76017071846973474894522159229723648233753001121635808031001847723939292218099
Line 203, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_max_rate/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/fusesoc-work/src/lowrisc_fpv_entropy_src_csr_assert_0/entropy_src_csr_assert_fpv.sv,306): (time 10198449 PS) Assertion tb.dut.entropy_src_csr_assert.conf_rd_A has failed
UVM_ERROR @ 10198449 ps: (entropy_src_csr_assert_fpv.sv:306) [ASSERT FAILED] conf_rd_A
UVM_INFO @ 10198449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:* has 1 failures:
0.entropy_src_stress_all.24484811900535072083299889360354315013990159632048010582967867759824542413491
Line 250, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_stress_all/latest/run.log
UVM_ERROR @ 1195344665 ps: (cip_base_scoreboard.sv:354) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_alert did not trigger max_delay:0
UVM_INFO @ 1195344665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---