HMAC Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.940s 1.849ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.560s 71.887us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.720s 30.914us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.060s 933.540us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.890s 56.308us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.010s 35.162us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.720s 30.914us 1 1 100.00
hmac_csr_aliasing 2.890s 56.308us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 3.840s 346.879us 1 1 100.00
V2 back_pressure hmac_back_pressure 12.710s 295.479us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.102m 128.549ms 1 1 100.00
hmac_test_sha384_vectors 5.695m 11.360ms 1 1 100.00
hmac_test_sha512_vectors 19.230s 1.715ms 1 1 100.00
hmac_test_hmac256_vectors 6.900s 478.381us 1 1 100.00
hmac_test_hmac384_vectors 8.500s 262.836us 1 1 100.00
hmac_test_hmac512_vectors 9.120s 305.859us 1 1 100.00
V2 burst_wr hmac_burst_wr 13.100s 2.781ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 10.708m 9.345ms 1 1 100.00
V2 error hmac_error 42.230s 1.184ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 40.130s 3.496ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.940s 1.849ms 1 1 100.00
hmac_long_msg 3.840s 346.879us 1 1 100.00
hmac_back_pressure 12.710s 295.479us 1 1 100.00
hmac_datapath_stress 10.708m 9.345ms 1 1 100.00
hmac_burst_wr 13.100s 2.781ms 1 1 100.00
hmac_stress_all 1.181m 2.151ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.940s 1.849ms 1 1 100.00
hmac_long_msg 3.840s 346.879us 1 1 100.00
hmac_back_pressure 12.710s 295.479us 1 1 100.00
hmac_datapath_stress 10.708m 9.345ms 1 1 100.00
hmac_wipe_secret 40.130s 3.496ms 1 1 100.00
hmac_test_sha256_vectors 3.102m 128.549ms 1 1 100.00
hmac_test_sha384_vectors 5.695m 11.360ms 1 1 100.00
hmac_test_sha512_vectors 19.230s 1.715ms 1 1 100.00
hmac_test_hmac256_vectors 6.900s 478.381us 1 1 100.00
hmac_test_hmac384_vectors 8.500s 262.836us 1 1 100.00
hmac_test_hmac512_vectors 9.120s 305.859us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.940s 1.849ms 1 1 100.00
hmac_long_msg 3.840s 346.879us 1 1 100.00
hmac_back_pressure 12.710s 295.479us 1 1 100.00
hmac_datapath_stress 10.708m 9.345ms 1 1 100.00
hmac_burst_wr 13.100s 2.781ms 1 1 100.00
hmac_error 42.230s 1.184ms 1 1 100.00
hmac_wipe_secret 40.130s 3.496ms 1 1 100.00
hmac_test_sha256_vectors 3.102m 128.549ms 1 1 100.00
hmac_test_sha384_vectors 5.695m 11.360ms 1 1 100.00
hmac_test_sha512_vectors 19.230s 1.715ms 1 1 100.00
hmac_test_hmac256_vectors 6.900s 478.381us 1 1 100.00
hmac_test_hmac384_vectors 8.500s 262.836us 1 1 100.00
hmac_test_hmac512_vectors 9.120s 305.859us 1 1 100.00
hmac_stress_all 1.181m 2.151ms 1 1 100.00
V2 stress_all hmac_stress_all 1.181m 2.151ms 1 1 100.00
V2 alert_test hmac_alert_test 1.440s 48.244us 1 1 100.00
V2 intr_test hmac_intr_test 1.490s 14.178us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.490s 403.076us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.490s 403.076us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.560s 71.887us 1 1 100.00
hmac_csr_rw 1.720s 30.914us 1 1 100.00
hmac_csr_aliasing 2.890s 56.308us 1 1 100.00
hmac_same_csr_outstanding 2.750s 142.681us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.560s 71.887us 1 1 100.00
hmac_csr_rw 1.720s 30.914us 1 1 100.00
hmac_csr_aliasing 2.890s 56.308us 1 1 100.00
hmac_same_csr_outstanding 2.750s 142.681us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.750s 354.115us 1 1 100.00
hmac_tl_intg_err 2.420s 263.068us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.420s 263.068us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.940s 1.849ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.030s 27.305us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.562m 11.542ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.740s 99.540us 1 1 100.00
TOTAL 28 28 100.00