I2C Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: `4ec736f`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	14.640s	4.953ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.970s	1.645ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.600s	31.854us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.530s	176.566us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.750s	4.583ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.830s	122.208us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.590s	44.207us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.530s	176.566us	1	1	100.00
		i2c_csr_aliasing	1.830s	122.208us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	5.140s	701.181us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	3.716m	56.280ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.600m	6.879ms	1	1	100.00
V2	host_override	i2c_host_override	1.480s	296.497us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.134m	18.328ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.214m	8.492ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.080s	149.595us	1	1	100.00
		i2c_host_fifo_fmt_empty	11.060s	315.199us	1	1	100.00
		i2c_host_fifo_reset_rx	4.290s	225.065us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	48.740s	5.387ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	26.050s	11.371ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.940s	343.388us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.150s	11.043ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	23.620s	13.957ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.000s	1.700ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	18.110s	1.488ms	1	1	100.00
		i2c_target_intr_smoke	5.210s	15.544ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.080s	271.292us	1	1	100.00
		i2c_target_fifo_reset_tx	1.880s	218.429us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	5.210s	8.609ms	1	1	100.00
		i2c_target_stress_rd	18.110s	1.488ms	1	1	100.00
		i2c_target_intr_stress_wr	3.583m	20.429ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.460s	960.468us	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.640s	1.081ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.820s	589.178us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.310s	714.431us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.660s	988.119us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.670s	123.896us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.600m	6.879ms	1	1	100.00
		i2c_host_perf_precise	1.117m	2.429ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	26.050s	11.371ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.770s	139.046us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.960s	2.185ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.750s	1.839ms	1	1	100.00
		i2c_target_nack_txstretch	2.050s	464.998us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.480s	1.222ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.660s	1.637ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.430s	17.489us	1	1	100.00
V2	intr_test	i2c_intr_test	1.530s	37.300us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.810s	51.983us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.810s	51.983us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.600s	31.854us	1	1	100.00
		i2c_csr_rw	1.530s	176.566us	1	1	100.00
		i2c_csr_aliasing	1.830s	122.208us	1	1	100.00
		i2c_same_csr_outstanding	1.810s	32.726us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.600s	31.854us	1	1	100.00
		i2c_csr_rw	1.530s	176.566us	1	1	100.00
		i2c_csr_aliasing	1.830s	122.208us	1	1	100.00
		i2c_same_csr_outstanding	1.810s	32.726us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.600s	246.991us	1	1	100.00
		i2c_sec_cm	1.770s	47.751us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.600s	246.991us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	23.350s	1.430ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.810s	1.030ms	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.350s	1.972ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.31360344477955949829336652189027098636773920757766503159063442908636885483457
Line 186, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 56280151375 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4505432

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.75843523044325284223571084514900922355822460775252175863312185644866049850491
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 343387887 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @14481

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.56025303329142749561620337190468141121671537069265010281843219986445105513520
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1029885322 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1029885322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.93061299450619020119119311946841110482396110068443644729468829650545490129532
    Line 97, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1430097210 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1430097210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.79085787366216545934378893312551181010650681205140326439646485436511212333611
    Line 108, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1971842733 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 220 [0xdc])
  UVM_INFO @ 1971842733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```