KEYMGR Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	19.910s	1.289ms	1	1	100.00
V1	random	keymgr_random	5.710s	294.743us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.820s	133.291us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.800s	35.489us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.800s	1.031ms	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	5.940s	485.464us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.800s	9.181us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.800s	35.489us	1	1	100.00
		keymgr_csr_aliasing	5.940s	485.464us	1	1	100.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	3.270s	39.217us	1	1	100.00
V2	sideload	keymgr_sideload	3.570s	520.149us	1	1	100.00
		keymgr_sideload_kmac	4.480s	177.523us	1	1	100.00
		keymgr_sideload_aes	9.080s	519.304us	1	1	100.00
		keymgr_sideload_otbn	2.450s	23.831us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	7.510s	945.769us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	4.000s	368.177us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.350s	30.293us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	2.580s	113.987us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.530s	144.295us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.710s	195.988us	1	1	100.00
V2	stress_all	keymgr_stress_all	4.550s	316.124us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.710s	10.524us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.730s	51.868us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.140s	69.067us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.140s	69.067us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.820s	133.291us	1	1	100.00
		keymgr_csr_rw	1.800s	35.489us	1	1	100.00
		keymgr_csr_aliasing	5.940s	485.464us	1	1	100.00
		keymgr_same_csr_outstanding	2.450s	69.544us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.820s	133.291us	1	1	100.00
		keymgr_csr_rw	1.800s	35.489us	1	1	100.00
		keymgr_csr_aliasing	5.940s	485.464us	1	1	100.00
		keymgr_same_csr_outstanding	2.450s	69.544us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	7.170s	297.807us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	7.170s	297.807us	1	1	100.00
		keymgr_tl_intg_err	3.470s	399.172us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.850s	71.023us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.850s	71.023us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.850s	71.023us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.850s	71.023us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.730s	7.411us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	7.170s	297.807us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	7.170s	297.807us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.470s	399.172us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.850s	71.023us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.270s	39.217us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	5.710s	294.743us	1	1	100.00
		keymgr_csr_rw	1.800s	35.489us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	5.710s	294.743us	1	1	100.00
		keymgr_csr_rw	1.800s	35.489us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	5.710s	294.743us	1	1	100.00
		keymgr_csr_rw	1.800s	35.489us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	4.000s	368.177us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.530s	144.295us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.530s	144.295us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	5.710s	294.743us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.980s	52.192us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	7.170s	297.807us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	7.170s	297.807us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	7.170s	297.807us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.690s	173.957us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	4.000s	368.177us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	7.170s	297.807us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	7.170s	297.807us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	7.170s	297.807us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.690s	173.957us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.690s	173.957us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	7.170s	297.807us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.690s	173.957us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	7.170s	297.807us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.690s	173.957us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	7.720s	193.566us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	30	90.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.113760061409772122947913910929696835436240602700997580086613254559467875236531
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
        UVM_ERROR @   7410638 ps: (keymgr_csr_assert_fpv.sv:484) [ASSERT FAILED] attest_sw_binding_6_rd_A
        UVM_INFO @   7410638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.69545099726771570985722922444497384668322800192245615291684015168430298943448
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
        UVM_ERROR @ 1030628168 ps: (keymgr_csr_assert_fpv.sv:418) [ASSERT FAILED] sealing_sw_binding_3_rd_A
        UVM_INFO @ 1030628168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.64373867293660928707689316709925591929691138596796415725868452302649195482052
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
        UVM_ERROR @   9181219 ps: (keymgr_csr_assert_fpv.sv:484) [ASSERT FAILED] attest_sw_binding_6_rd_A
        UVM_INFO @   9181219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---