KMAC/UNMASKED Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	38.880s	8.102ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.680s	52.577us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.580s	64.973us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.380s	4.953ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.740s	482.374us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.940s	60.570us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.580s	64.973us	1	1	100.00
		kmac_csr_aliasing	6.740s	482.374us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.390s	16.066us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.870s	203.629us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	40.917m	94.724ms	1	1	100.00
V2	burst_write	kmac_burst_write	25.100s	6.855ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.710s	9.459ms	1	1	100.00
		kmac_test_vectors_sha3_256	20.190s	564.609us	1	1	100.00
		kmac_test_vectors_sha3_384	14.710s	425.530us	1	1	100.00
		kmac_test_vectors_sha3_512	11.315m	74.759ms	1	1	100.00
		kmac_test_vectors_shake_128	2.200m	11.099ms	1	1	100.00
		kmac_test_vectors_shake_256	24.253m	317.649ms	1	1	100.00
		kmac_test_vectors_kmac	2.610s	191.274us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.750s	113.639us	1	1	100.00
V2	sideload	kmac_sideload	3.386m	12.928ms	1	1	100.00
V2	app	kmac_app	1.279m	2.117ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	12.050s	2.886ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.119m	3.933ms	1	1	100.00
V2	error	kmac_error	39.540s	3.832ms	1	1	100.00
V2	key_error	kmac_key_error	2.740s	418.459us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.280s	374.167us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	16.020s	1.189ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	24.540s	2.024ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	15.080s	2.492ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.860s	59.889us	1	1	100.00
V2	stress_all	kmac_stress_all	49.980s	4.148ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.530s	16.787us	1	1	100.00
V2	alert_test	kmac_alert_test	1.410s	35.542us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.310s	284.530us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.310s	284.530us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.680s	52.577us	1	1	100.00
		kmac_csr_rw	1.580s	64.973us	1	1	100.00
		kmac_csr_aliasing	6.740s	482.374us	1	1	100.00
		kmac_same_csr_outstanding	2.730s	489.758us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.680s	52.577us	1	1	100.00
		kmac_csr_rw	1.580s	64.973us	1	1	100.00
		kmac_csr_aliasing	6.740s	482.374us	1	1	100.00
		kmac_same_csr_outstanding	2.730s	489.758us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.700s	69.419us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.700s	69.419us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.700s	69.419us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.700s	69.419us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.680s	1.057ms	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	43.760s	18.141ms	1	1	100.00
		kmac_tl_intg_err	4.120s	3.120ms	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.120s	3.120ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.860s	59.889us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	38.880s	8.102ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.386m	12.928ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.700s	69.419us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	43.760s	18.141ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	43.760s	18.141ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	43.760s	18.141ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	38.880s	8.102ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.860s	59.889us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	43.760s	18.141ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	27.900s	10.064ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	38.880s	8.102ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	41.460s	2.854ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.89192803846295970330133633519422516165337883866247641720939416849597837959629
      Line 119, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2853645722 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2853645722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---