OTBN Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	52.000s	148.107us	1	1	100.00
V1	single_binary	otbn_single	39.000s	16.991us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	45.169us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	38.468us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	96.584us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	53.056us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	106.635us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	38.468us	1	1	100.00
		otbn_csr_aliasing	7.000s	53.056us	1	1	100.00
V1	mem_walk	otbn_mem_walk	13.000s	361.243us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	15.000s	870.176us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	45.000s	181.629us	1	1	100.00
V2	multi_error	otbn_multi_err	1.800m	495.301us	1	1	100.00
V2	back_to_back	otbn_multi	1.233m	912.475us	1	1	100.00
V2	stress_all	otbn_stress_all	40.000s	142.649us	1	1	100.00
V2	lc_escalation	otbn_escalate	15.000s	48.827us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	38.246us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	8.000s	37.126us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	57.373us	1	1	100.00
V2	intr_test	otbn_intr_test	5.000s	203.398us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	64.953us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	64.953us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	45.169us	1	1	100.00
		otbn_csr_rw	6.000s	38.468us	1	1	100.00
		otbn_csr_aliasing	7.000s	53.056us	1	1	100.00
		otbn_same_csr_outstanding	5.000s	44.923us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	45.169us	1	1	100.00
		otbn_csr_rw	6.000s	38.468us	1	1	100.00
		otbn_csr_aliasing	7.000s	53.056us	1	1	100.00
		otbn_same_csr_outstanding	5.000s	44.923us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	15.000s	49.521us	1	1	100.00
		otbn_dmem_err	8.000s	52.200us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	59.683us	1	1	100.00
		otbn_controller_ispr_rdata_err	11.000s	112.410us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	65.570us	1	1	100.00
		otbn_urnd_err	10.000s	60.377us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	10.399us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	26.400us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	14.841us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	5.967m	2.364ms	1	1	100.00
		otbn_tl_intg_err	19.000s	122.098us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	22.000s	648.482us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	5.967m	2.364ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	5.967m	2.364ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	52.000s	148.107us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	8.000s	52.200us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	15.000s	49.521us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	19.000s	122.098us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	15.000s	48.827us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	15.000s	49.521us	1	1	100.00
		otbn_dmem_err	8.000s	52.200us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	38.246us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	10.399us	1	1	100.00
		otbn_sec_cm	5.967m	2.364ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.967m	2.364ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	39.000s	16.991us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	15.000s	49.521us	1	1	100.00
		otbn_dmem_err	8.000s	52.200us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	38.246us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	10.399us	1	1	100.00
		otbn_sec_cm	5.967m	2.364ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.967m	2.364ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	15.000s	48.827us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	15.000s	49.521us	1	1	100.00
		otbn_dmem_err	8.000s	52.200us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	38.246us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	10.399us	1	1	100.00
		otbn_sec_cm	5.967m	2.364ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.967m	2.364ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	39.000s	16.991us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	32.247us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	463.118us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	21.000s	92.541us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	21.000s	92.541us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	16.000s	52.678us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.967m	2.364ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.967m	2.364ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	10.000s	56.897us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.967m	2.364ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.967m	2.364ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	20.582us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	20.582us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	8.000s	147.879us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	39.000s	16.991us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	39.000s	16.991us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	39.000s	16.991us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.233m	912.475us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	39.000s	16.991us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	39.000s	16.991us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	8.000s	235.937us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	39.000s	16.991us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.967m	2.364ms	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.483m	2.004ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.70076980816037725581426778117474133608027380929031391522700524574604112562850
      Line 314, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2003566706 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2003566706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.67586067168744123509899431685477464584772998438918504489268442982592597160
      Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 147879003 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @ 147879003 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @ 147879003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---