PATTGEN Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	16.000s	71.745us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	41.394us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	5.000s	58.421us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	248.917us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	40.734us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	24.838us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	5.000s	58.421us	1	1	100.00
		pattgen_csr_aliasing	4.000s	40.734us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf			0	1	0.00
V2	cnt_rollover	cnt_rollover	42.000s	5.401ms	1	1	100.00
V2	error	pattgen_error	15.000s	96.863us	1	1	100.00
V2	stress_all	pattgen_stress_all	9.033m	25.724ms	0	1	0.00
V2	alert_test	pattgen_alert_test	4.000s	17.624us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	33.562us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	89.437us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	89.437us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	41.394us	1	1	100.00
		pattgen_csr_rw	5.000s	58.421us	1	1	100.00
		pattgen_csr_aliasing	4.000s	40.734us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	20.978us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	41.394us	1	1	100.00
		pattgen_csr_rw	5.000s	58.421us	1	1	100.00
		pattgen_csr_aliasing	4.000s	40.734us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	20.978us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	164.223us	1	1	100.00
		pattgen_sec_cm	10.000s	47.539us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	164.223us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	42.000s	20.774ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	11.000s	32.711us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test pattgen_perf has 1 failures.

    • 0.pattgen_perf.77603873926676255453819442909620000925361959231250986931599552335301226768665
      Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.88133366465207597565873617419522359675691049085778539599305888269870438352234
      Line 215, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7211570040 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 7211571970 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 7211571970 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 3/10
        UVM_INFO @ 7211810065 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.114518284685039603206804610178886934655133391807694365445320875124270721111552
      Line 139, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        UVM_ERROR @ 25723897490 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
        --------------------------------------
        Name        Type          Size  Value
        --------------------------------------
        exp_item    pattgen_item  -     @22401