ROM_CTRL/32KB Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.860s 180.848us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.710s 2.042ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.680s 386.465us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.930s 165.210us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.420s 534.707us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.500s 1.055ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.680s 386.465us 1 1 100.00
rom_ctrl_csr_aliasing 4.420s 534.707us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.110s 168.781us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.940s 306.999us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.320s 402.771us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 15.840s 1.215ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.700s 225.549us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.160s 167.830us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.210s 374.432us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.210s 374.432us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.710s 2.042ms 1 1 100.00
rom_ctrl_csr_rw 4.680s 386.465us 1 1 100.00
rom_ctrl_csr_aliasing 4.420s 534.707us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.410s 127.006us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.710s 2.042ms 1 1 100.00
rom_ctrl_csr_rw 4.680s 386.465us 1 1 100.00
rom_ctrl_csr_aliasing 4.420s 534.707us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.410s 127.006us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 46.690s 1.825ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 15.650s 1.132ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.942m 733.137us 1 1 100.00
rom_ctrl_tl_intg_err 21.140s 208.761us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.942m 733.137us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.942m 733.137us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 46.690s 1.825ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 46.690s 1.825ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 46.690s 1.825ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 46.690s 1.825ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 46.690s 1.825ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.942m 733.137us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.942m 733.137us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.860s 180.848us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.860s 180.848us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.860s 180.848us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 21.140s 208.761us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 46.690s 1.825ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.700s 225.549us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 46.690s 1.825ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 46.690s 1.825ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 46.690s 1.825ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 15.650s 1.132ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.942m 733.137us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 4.296m 3.418ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00