| V1 |
random |
rv_timer_random |
1.700s |
14.591us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
1.470s |
207.944us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
1.690s |
27.395us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
3.390s |
284.113us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
1.660s |
28.302us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
1.590s |
51.266us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
1.690s |
27.395us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.660s |
28.302us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
1.540s |
222.599us |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
3.370s |
1.748ms |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
6.711m |
956.198ms |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
6.711m |
956.198ms |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
2.820s |
1.041ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
1.420s |
27.348us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
1.330s |
12.884us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
2.510s |
259.553us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
2.510s |
259.553us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
1.470s |
207.944us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.690s |
27.395us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.660s |
28.302us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.670s |
43.019us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
1.470s |
207.944us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.690s |
27.395us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.660s |
28.302us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.670s |
43.019us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
1.850s |
404.768us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
1.980s |
320.071us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
1.980s |
320.071us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
1.450s |
43.193us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
1.800s |
16.839us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
22.510s |
7.641ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |