SPI_DEVICE/1R1W Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	15.210s	4.155ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.990s	51.678us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.930s	36.362us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	21.300s	546.899us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.790s	3.217ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.710s	457.983us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.930s	36.362us	1	1	100.00
		spi_device_csr_aliasing	15.790s	3.217ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.570s	16.096us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.130s	38.048us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.550s	23.240us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.380s	2.090us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.440s	6.848us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.670s	110.541us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.670s	110.541us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.160s	2.464ms	1	1	100.00
		spi_device_tpm_sts_read	1.530s	86.698us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.470s	111.610us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	9.450s	3.773ms	1	1	100.00
		spi_device_flash_all	13.670s	1.153ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	15.040s	14.611ms	1	1	100.00
		spi_device_flash_all	13.670s	1.153ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	15.040s	14.611ms	1	1	100.00
		spi_device_flash_all	13.670s	1.153ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	13.670s	1.153ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.480s	485.293us	1	1	100.00
		spi_device_flash_all	13.670s	1.153ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.480s	485.293us	1	1	100.00
		spi_device_flash_all	13.670s	1.153ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.480s	485.293us	1	1	100.00
		spi_device_flash_all	13.670s	1.153ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.480s	485.293us	1	1	100.00
		spi_device_flash_all	13.670s	1.153ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.480s	485.293us	1	1	100.00
		spi_device_flash_all	13.670s	1.153ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.880s	2.987ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	11.110s	11.899ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	11.110s	11.899ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	11.110s	11.899ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.870s	3.920ms	1	1	100.00
		spi_device_read_buffer_direct	5.420s	727.580us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	11.110s	11.899ms	1	1	100.00
		spi_device_flash_all	13.670s	1.153ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	13.670s	1.153ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	13.670s	1.153ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.690s	47.282us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.690s	47.282us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	15.210s	4.155ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	56.040s	6.533ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.570s	189.068us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.400s	22.649us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.440s	27.365us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.490s	35.487us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.490s	35.487us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.990s	51.678us	1	1	100.00
		spi_device_csr_rw	1.930s	36.362us	1	1	100.00
		spi_device_csr_aliasing	15.790s	3.217ms	1	1	100.00
		spi_device_same_csr_outstanding	3.260s	279.354us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.990s	51.678us	1	1	100.00
		spi_device_csr_rw	1.930s	36.362us	1	1	100.00
		spi_device_csr_aliasing	15.790s	3.217ms	1	1	100.00
		spi_device_same_csr_outstanding	3.260s	279.354us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.820s	291.567us	1	1	100.00
		spi_device_tl_intg_err	11.340s	659.427us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.340s	659.427us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	41.760s	10.814ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.57124203219021091534922222859332889531598848140275330868783060824210059607474
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1715125 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[29])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1715125 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1715125 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[925])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.22099525254031292011193347529569507452709415264609088922684366225516099641430
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3977671 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x843a34 [100001000011101000110100] vs 0x0 [0])
        UVM_ERROR @   4013671 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdb3443 [110110110011010001000011] vs 0x0 [0])
        UVM_ERROR @   4113671 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6e65b6 [11011100110010110110110] vs 0x0 [0])
        UVM_ERROR @   4140671 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf5589c [111101010101100010011100] vs 0x0 [0])
        UVM_ERROR @   4209671 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x97220b [100101110010001000001011] vs 0x0 [0])