SPI_DEVICE/2P Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	40.470s	2.568ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.740s	75.550us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.080s	223.036us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.600s	1.567ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.480s	2.054ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.250s	412.198us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.080s	223.036us	1	1	100.00
		spi_device_csr_aliasing	15.480s	2.054ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.410s	12.609us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.040s	36.366us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.580s	106.016us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.940s	122.240us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.590s	16.323us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	2.440s	81.694us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.440s	81.694us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.050s	1.802ms	1	1	100.00
		spi_device_tpm_sts_read	1.450s	32.734us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	24.360s	20.352ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.180s	20.119ms	1	1	100.00
		spi_device_flash_all	3.542m	218.308ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	6.380s	28.711ms	1	1	100.00
		spi_device_flash_all	3.542m	218.308ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	6.380s	28.711ms	1	1	100.00
		spi_device_flash_all	3.542m	218.308ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	3.542m	218.308ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	8.310s	3.719ms	1	1	100.00
		spi_device_flash_all	3.542m	218.308ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	8.310s	3.719ms	1	1	100.00
		spi_device_flash_all	3.542m	218.308ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	8.310s	3.719ms	1	1	100.00
		spi_device_flash_all	3.542m	218.308ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	8.310s	3.719ms	1	1	100.00
		spi_device_flash_all	3.542m	218.308ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	8.310s	3.719ms	1	1	100.00
		spi_device_flash_all	3.542m	218.308ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.820s	453.581us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	34.330s	62.787ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	34.330s	62.787ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	34.330s	62.787ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.820s	95.019us	1	1	100.00
		spi_device_read_buffer_direct	4.700s	4.178ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	34.330s	62.787ms	1	1	100.00
		spi_device_flash_all	3.542m	218.308ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	3.542m	218.308ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	3.542m	218.308ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.290s	77.409us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.290s	77.409us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	40.470s	2.568ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.716m	68.146ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.700s	211.858us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.790s	18.304us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.560s	17.405us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.910s	1.448ms	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.910s	1.448ms	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.740s	75.550us	1	1	100.00
		spi_device_csr_rw	3.080s	223.036us	1	1	100.00
		spi_device_csr_aliasing	15.480s	2.054ms	1	1	100.00
		spi_device_same_csr_outstanding	4.410s	192.865us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.740s	75.550us	1	1	100.00
		spi_device_csr_rw	3.080s	223.036us	1	1	100.00
		spi_device_csr_aliasing	15.480s	2.054ms	1	1	100.00
		spi_device_same_csr_outstanding	4.410s	192.865us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.820s	154.732us	1	1	100.00
		spi_device_tl_intg_err	11.010s	543.028us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.010s	543.028us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	59.320s	29.050ms	1	1	100.00
		TOTAL			33	33	100.00