SRAM_CTRL/MAIN Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	6.600s	3.566ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.560s	24.061us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.510s	23.990us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.450s	163.434us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.570s	18.936us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.480s	1.815ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.510s	23.990us	1	1	100.00
		sram_ctrl_csr_aliasing	1.570s	18.936us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.879m	13.832ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.943m	23.169ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.479m	17.093ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.976m	3.412ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	17.351m	324.490ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	12.843m	22.382ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	23.030s	21.211ms	1	1	100.00
V2	executable	sram_ctrl_executable	10.403m	78.879ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	18.280s	2.789ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.317m	11.760ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	12.070s	2.701ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	1.042m	791.655us	1	1	100.00
		sram_ctrl_throughput_w_readback	9.700s	3.665ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.650m	10.135ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.300s	360.444us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	59.929m	204.926ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.590s	30.341us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.110s	234.802us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.110s	234.802us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.560s	24.061us	1	1	100.00
		sram_ctrl_csr_rw	1.510s	23.990us	1	1	100.00
		sram_ctrl_csr_aliasing	1.570s	18.936us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.720s	69.423us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.560s	24.061us	1	1	100.00
		sram_ctrl_csr_rw	1.510s	23.990us	1	1	100.00
		sram_ctrl_csr_aliasing	1.570s	18.936us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.720s	69.423us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	17.000s	3.793ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.510s	11.519us	0	1	0.00
		sram_ctrl_tl_intg_err	3.060s	217.447us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.510s	11.519us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.060s	217.447us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.650m	10.135ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.650m	10.135ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.510s	23.990us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	10.403m	78.879ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	10.403m	78.879ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	10.403m	78.879ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	23.030s	21.211ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.890s	821.541us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	17.000s	3.793ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.420s	2.636ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	6.600s	3.566ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	6.600s	3.566ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	10.403m	78.879ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.510s	11.519us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	23.030s	21.211ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.510s	11.519us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.510s	11.519us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	6.600s	3.566ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.510s	11.519us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.270s	341.611us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.79956478461691319026955092047091831339760112765233219539635748664758194414013
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 821541303 ps: (tlul_adapter_sram.sv:643) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 821541303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.82622072973661120295690720755997049216018985786526915952930525939710565873685
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  11518940 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  11518940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---