SRAM_CTRL/RET Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	40.500s	742.869us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.480s	41.193us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.550s	38.981us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.720s	50.738us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.460s	30.264us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.910s	158.399us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.550s	38.981us	1	1	100.00
		sram_ctrl_csr_aliasing	1.460s	30.264us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.270s	953.023us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.020s	90.875us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	23.770s	4.933ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.321m	12.566ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	31.910s	9.987ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.266m	1.098ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.060s	656.959us	1	1	100.00
V2	executable	sram_ctrl_executable	8.703m	13.712ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	31.410s	350.831us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.472m	11.387ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	54.990s	250.740us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	34.670s	265.921us	1	1	100.00
		sram_ctrl_throughput_w_readback	57.710s	4.640ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	11.077m	16.159ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.700s	103.575us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	5.050m	2.923ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.730s	23.968us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.010s	72.857us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.010s	72.857us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.480s	41.193us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	38.981us	1	1	100.00
		sram_ctrl_csr_aliasing	1.460s	30.264us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.520s	28.811us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.480s	41.193us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	38.981us	1	1	100.00
		sram_ctrl_csr_aliasing	1.460s	30.264us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.520s	28.811us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.660s	786.706us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.720s	3.081us	0	1	0.00
		sram_ctrl_tl_intg_err	3.070s	313.768us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.720s	3.081us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.070s	313.768us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	11.077m	16.159ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	11.077m	16.159ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.550s	38.981us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.703m	13.712ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.703m	13.712ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.703m	13.712ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.060s	656.959us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.040s	63.428us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.660s	786.706us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.010s	108.521us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	40.500s	742.869us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	40.500s	742.869us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.703m	13.712ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.720s	3.081us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.060s	656.959us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.720s	3.081us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.720s	3.081us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	40.500s	742.869us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.720s	3.081us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.942m	4.951ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.93117598542782242236599929212408580916252542929345734502410759869791446092410
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3081170 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3081170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---