SYSRST_CTRL Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 5.360s 2.113ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 6.920s 2.478ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 2.790s 2.219ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.810s 2.337ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 6.020s 4.033ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 3.560s 2.060ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 3.221m 76.153ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 9.570s 2.992ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 3.710s 2.060ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 3.560s 2.060ms 1 1 100.00
sysrst_ctrl_csr_aliasing 9.570s 2.992ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 3.772m 114.507ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 42.190s 45.470ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 8.570s 3.607ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 7.170s 3.365ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 6.240s 2.509ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 3.310s 2.175ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 8.690s 3.827ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 6.410s 2.610ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 4.270s 3.027ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.301m 40.275ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 22.850s 11.108ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 2.230s 2.036ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 3.800s 2.022ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.030s 2.176ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.030s 2.176ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 6.020s 4.033ms 1 1 100.00
sysrst_ctrl_csr_rw 3.560s 2.060ms 1 1 100.00
sysrst_ctrl_csr_aliasing 9.570s 2.992ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.070s 4.664ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 6.020s 4.033ms 1 1 100.00
sysrst_ctrl_csr_rw 3.560s 2.060ms 1 1 100.00
sysrst_ctrl_csr_aliasing 9.570s 2.992ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.070s 4.664ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 1.371m 42.013ms 1 1 100.00
sysrst_ctrl_tl_intg_err 42.730s 42.428ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 42.730s 42.428ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 11.610s 5.635ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00